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target/ppc: Inline gen_icount_io_start()

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Now that gen_icount_io_start() is a simple wrapper to
translator_io_start(), inline it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230602095439.48102-1-philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-06-02 11:54:39 +02:00 committed by Richard Henderson
parent dfd1b81274
commit 283a917772
3 changed files with 35 additions and 40 deletions
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10
target/ppc/power8-pmu-regs.c.inc
View File

@ -103,9 +103,9 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val)
/*
* helper_store_mmcr0 will make clock based operations that
* will cause 'bad icount read' errors if we do not execute
* gen_icount_io_start() beforehand.
* translator_io_start() beforehand.
*/
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_mmcr0(cpu_env, val);
/*
@ -179,7 +179,7 @@ void spr_read_PMC(DisasContext *ctx, int gprn, int sprn)
{
TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn);
}
@ -212,7 +212,7 @@ void spr_write_PMC(DisasContext *ctx, int sprn, int gprn)
{
TCGv_i32 t_sprn = tcg_constant_i32(sprn);
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]);
}
@ -248,7 +248,7 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn)
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]);
}
#else

63
target/ppc/translate.c
View File

@ -296,15 +296,10 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp,
ctx->base.is_jmp = DISAS_NORETURN;
}
static void gen_icount_io_start(DisasContext *ctx)
{
translator_io_start(&ctx->base);
}
#if !defined(CONFIG_USER_ONLY)
static void gen_ppc_maybe_interrupt(DisasContext *ctx)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_ppc_maybe_interrupt(cpu_env);
}
#endif
@ -541,13 +536,13 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
}
void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
}
#endif
@ -556,13 +551,13 @@ void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
/* Time base */
void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
}
void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
}
@ -579,13 +574,13 @@ void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
#if !defined(CONFIG_USER_ONLY)
void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
}
void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
}
@ -602,44 +597,44 @@ void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
#if defined(TARGET_PPC64)
void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
}
void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
}
/* HDECR */
void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
}
void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
}
void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
}
void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
}
void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
}
@ -784,19 +779,19 @@ void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
#if !defined(CONFIG_USER_ONLY)
void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
}
void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
}
void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_store_spr(sprn, cpu_gpr[gprn]);
gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
/* We must stop translation as we may have rebooted */
@ -805,19 +800,19 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
}
void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]);
}
void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]);
}
@ -830,13 +825,13 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn)
void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
}
void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
{
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
}
#endif
@ -2462,7 +2457,7 @@ static void gen_darn(DisasContext *ctx)
if (l > 2) {
tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1);
} else {
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
if (l == 0) {
gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]);
} else {
@ -4056,7 +4051,7 @@ static void pmu_count_insns(DisasContext *ctx)
* running with icount and we do not handle it beforehand,
* the helper can trigger a 'bad icount read'.
*/
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
/* Avoid helper calls when only PMC5-6 are enabled. */
if (!ctx->pmc_other) {
@ -4369,7 +4364,7 @@ static void gen_rfi(DisasContext *ctx)
}
/* Restore CPU state */
CHK_SV(ctx);
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfi(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@ -4384,7 +4379,7 @@ static void gen_rfid(DisasContext *ctx)
#else
/* Restore CPU state */
CHK_SV(ctx);
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfid(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@ -4399,7 +4394,7 @@ static void gen_rfscv(DisasContext *ctx)
#else
/* Restore CPU state */
CHK_SV(ctx);
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfscv(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@ -4724,7 +4719,7 @@ static void gen_mtmsrd(DisasContext *ctx)
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
if (ctx->opcode & 0x00010000) {
/* L=1 form only updates EE and RI */
@ -4764,7 +4759,7 @@ static void gen_mtmsr(DisasContext *ctx)
t0 = tcg_temp_new();
t1 = tcg_temp_new();
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
if (ctx->opcode & 0x00010000) {
/* L=1 form only updates EE and RI */
mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE);

2
target/ppc/translate/branch-impl.c.inc
View File

@ -16,7 +16,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg)
{
REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
gen_icount_io_start(ctx);
translator_io_start(&ctx->base);
gen_update_cfar(ctx, ctx->cia);
gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]);