mips_malta: Add setting up GT64120 BARs to the nanoMIPS bootloader
Setup the GT64120 BARs in the nanoMIPS bootloader, in the same way that they are setup in the MIPS32 bootloader. This is necessary for Linux to be able to access peripherals, including the UART. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Paul Burton <pburton@wavecomp.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
This commit is contained in:
Paul Burton
Aleksandar Markovic
parent
ce3940ccca
commit
28861af8e9
@ -609,47 +609,190 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr,
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#define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
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#define NM_HI2(VAL) \
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(((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
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(((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
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#define NM_LO(VAL) ((VAL) & 0xfff)
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stw_p(p++, 0x2800); stw_p(p++, 0x001c); /* bc to_here */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000); /* nop */
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stw_p(p++, 0x2800); stw_p(p++, 0x001c);
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/* bc to_here */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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stw_p(p++, 0x8000); stw_p(p++, 0xc000);
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/* nop */
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/* to_here: */
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stw_p(p++, 0x0080); stw_p(p++, 0x0002); /* li a0,2 */
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stw_p(p++, 0x0080); stw_p(p++, 0x0002);
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/* li a0,2 */
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stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64));
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stw_p(p++, NM_HI2(ENVP_ADDR - 64));
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/* lui sp,%hi(ENVP_ADDR - 64) */
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/* lui sp,%hi(ENVP_ADDR - 64) */
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stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64));
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/* ori sp,sp,%lo(ENVP_ADDR - 64) */
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stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR));
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stw_p(p++, NM_HI2(ENVP_ADDR));
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/* lui a1,%hi(ENVP_ADDR) */
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/* lui a1,%hi(ENVP_ADDR) */
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stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR));
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/* ori a1,a1,%lo(ENVP_ADDR) */
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/* ori a1,a1,%lo(ENVP_ADDR) */
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stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8));
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stw_p(p++, NM_HI2(ENVP_ADDR + 8));
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/* lui a2,%hi(ENVP_ADDR + 8) */
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/* lui a2,%hi(ENVP_ADDR + 8) */
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stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8));
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/* ori a2,a2,%lo(ENVP_ADDR + 8) */
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stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size));
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stw_p(p++, NM_HI2(loaderparams.ram_low_size));
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/* lui a3,%hi(loaderparams.ram_low_size) */
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stw_p(p++, 0x80e7); stw_p(p++, NM_LO(loaderparams.ram_low_size));
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/* ori a3,a3,%lo(loaderparams.ram_low_size) */
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/*
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* Load BAR registers as done by YAMON:
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*
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* - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
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* - set up PCI0 MEM0 at 0x10000000, size 0x8000000
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* - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
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*
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*/
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stw_p(p++, 0xe040); stw_p(p++, 0x0681);
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/* lui t1, %hi(0xb4000000) */
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#ifdef TARGET_WORDS_BIGENDIAN
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stw_p(p++, 0xe020); stw_p(p++, 0x0be1);
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/* lui t0, %hi(0xdf000000) */
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/* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
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stw_p(p++, 0x8422); stw_p(p++, 0x9068);
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/* sw t0, 0x68(t1) */
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stw_p(p++, 0xe040); stw_p(p++, 0x077d);
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/* lui t1, %hi(0xbbe00000) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0801);
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/* lui t0, %hi(0xc0000000) */
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/* 0x48 corresponds to GT_PCI0IOLD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9048);
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/* sw t0, 0x48(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0800);
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/* lui t0, %hi(0x40000000) */
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/* 0x50 corresponds to GT_PCI0IOHD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9050);
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/* sw t0, 0x50(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0001);
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/* lui t0, %hi(0x80000000) */
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/* 0x58 corresponds to GT_PCI0M0LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9058);
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/* sw t0, 0x58(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x07e0);
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/* lui t0, %hi(0x3f000000) */
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/* 0x60 corresponds to GT_PCI0M0HD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9060);
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/* sw t0, 0x60(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0821);
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/* lui t0, %hi(0xc1000000) */
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/* 0x80 corresponds to GT_PCI0M1LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9080);
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/* sw t0, 0x80(t1) */
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stw_p(p++, 0xe020); stw_p(p++, 0x0bc0);
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/* lui t0, %hi(0x5e000000) */
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#else
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stw_p(p++, 0x0020); stw_p(p++, 0x00df);
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/* addiu[32] t0, $0, 0xdf */
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/* 0x68 corresponds to GT_ISD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9068);
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/* sw t0, 0x68(t1) */
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/* Use kseg2 remapped address 0x1be00000 */
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stw_p(p++, 0xe040); stw_p(p++, 0x077d);
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/* lui t1, %hi(0xbbe00000) */
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stw_p(p++, 0x0020); stw_p(p++, 0x00c0);
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/* addiu[32] t0, $0, 0xc0 */
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/* 0x48 corresponds to GT_PCI0IOLD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9048);
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/* sw t0, 0x48(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x0040);
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/* addiu[32] t0, $0, 0x40 */
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/* 0x50 corresponds to GT_PCI0IOHD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9050);
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/* sw t0, 0x50(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x0080);
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/* addiu[32] t0, $0, 0x80 */
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/* 0x58 corresponds to GT_PCI0M0LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9058);
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/* sw t0, 0x58(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x003f);
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/* addiu[32] t0, $0, 0x3f */
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/* 0x60 corresponds to GT_PCI0M0HD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9060);
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/* sw t0, 0x60(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x00c1);
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/* addiu[32] t0, $0, 0xc1 */
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/* 0x80 corresponds to GT_PCI0M1LD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9080);
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/* sw t0, 0x80(t1) */
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stw_p(p++, 0x0020); stw_p(p++, 0x005e);
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/* addiu[32] t0, $0, 0x5e */
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#endif
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/* 0x88 corresponds to GT_PCI0M1HD */
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stw_p(p++, 0x8422); stw_p(p++, 0x9088);
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/* sw t0, 0x88(t1) */
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stw_p(p++, 0xe320 | NM_HI1(kernel_entry));
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stw_p(p++, NM_HI2(kernel_entry));
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/* lui t9,%hi(kernel_entry) */
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/* lui t9,%hi(kernel_entry) */
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stw_p(p++, 0x8339); stw_p(p++, NM_LO(kernel_entry));
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/* ori t9,t9,%lo(kernel_entry) */
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/* ori t9,t9,%lo(kernel_entry) */
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stw_p(p++, 0x4bf9); stw_p(p++, 0x0000);
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/* jalrc t8 */
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/* jalrc t8 */
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}
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/* ROM and pseudo bootloader
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