aspeed: add support for the Aspeed MII controller of the AST2600
The AST2600 SoC has an extra controller to set the PHY registers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 20190925143248.10000-23-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater
Peter Maydell
parent
d300db0277
commit
289251b033
@ -31,6 +31,10 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
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[ASPEED_FMC] = 0x1E620000,
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[ASPEED_SPI1] = 0x1E630000,
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[ASPEED_SPI2] = 0x1E641000,
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[ASPEED_MII1] = 0x1E650000,
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[ASPEED_MII2] = 0x1E650008,
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[ASPEED_MII3] = 0x1E650010,
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[ASPEED_MII4] = 0x1E650018,
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[ASPEED_ETH1] = 0x1E660000,
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[ASPEED_ETH3] = 0x1E670000,
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[ASPEED_ETH2] = 0x1E680000,
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@ -181,6 +185,12 @@ static void aspeed_soc_ast2600_init(Object *obj)
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for (i = 0; i < sc->macs_num; i++) {
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sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
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sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
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sysbus_init_child_obj(obj, "mii[*]", &s->mii[i], sizeof(s->mii[i]),
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TYPE_ASPEED_MII);
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object_property_add_const_link(OBJECT(&s->mii[i]), "nic",
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OBJECT(&s->ftgmac100[i]),
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&error_abort);
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}
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sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
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@ -417,6 +427,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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sc->memmap[ASPEED_ETH1 + i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
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aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
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object_property_set_bool(OBJECT(&s->mii[i]), true, "realized",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->mii[i]), 0,
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sc->memmap[ASPEED_MII1 + i]);
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}
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/* XDMA */
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@ -15,6 +15,7 @@
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#include "hw/irq.h"
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#include "hw/net/ftgmac100.h"
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#include "sysemu/dma.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "net/checksum.h"
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@ -1087,9 +1088,170 @@ static const TypeInfo ftgmac100_info = {
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.class_init = ftgmac100_class_init,
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};
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/*
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* AST2600 MII controller
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*/
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#define ASPEED_MII_PHYCR_FIRE BIT(31)
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#define ASPEED_MII_PHYCR_ST_22 BIT(28)
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#define ASPEED_MII_PHYCR_OP(x) ((x) & (ASPEED_MII_PHYCR_OP_WRITE | \
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ASPEED_MII_PHYCR_OP_READ))
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#define ASPEED_MII_PHYCR_OP_WRITE BIT(26)
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#define ASPEED_MII_PHYCR_OP_READ BIT(27)
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#define ASPEED_MII_PHYCR_DATA(x) (x & 0xffff)
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#define ASPEED_MII_PHYCR_PHY(x) (((x) >> 21) & 0x1f)
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#define ASPEED_MII_PHYCR_REG(x) (((x) >> 16) & 0x1f)
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#define ASPEED_MII_PHYDATA_IDLE BIT(16)
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static void aspeed_mii_transition(AspeedMiiState *s, bool fire)
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{
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if (fire) {
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s->phycr |= ASPEED_MII_PHYCR_FIRE;
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s->phydata &= ~ASPEED_MII_PHYDATA_IDLE;
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} else {
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s->phycr &= ~ASPEED_MII_PHYCR_FIRE;
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s->phydata |= ASPEED_MII_PHYDATA_IDLE;
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}
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}
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static void aspeed_mii_do_phy_ctl(AspeedMiiState *s)
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{
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uint8_t reg;
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uint16_t data;
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if (!(s->phycr & ASPEED_MII_PHYCR_ST_22)) {
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aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
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qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
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return;
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}
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/* Nothing to do */
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if (!(s->phycr & ASPEED_MII_PHYCR_FIRE)) {
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return;
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}
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reg = ASPEED_MII_PHYCR_REG(s->phycr);
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data = ASPEED_MII_PHYCR_DATA(s->phycr);
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switch (ASPEED_MII_PHYCR_OP(s->phycr)) {
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case ASPEED_MII_PHYCR_OP_WRITE:
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do_phy_write(s->nic, reg, data);
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break;
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case ASPEED_MII_PHYCR_OP_READ:
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s->phydata = (s->phydata & ~0xffff) | do_phy_read(s->nic, reg);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
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__func__, s->phycr);
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}
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aspeed_mii_transition(s, !ASPEED_MII_PHYCR_FIRE);
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}
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static uint64_t aspeed_mii_read(void *opaque, hwaddr addr, unsigned size)
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{
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AspeedMiiState *s = ASPEED_MII(opaque);
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switch (addr) {
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case 0x0:
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return s->phycr;
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case 0x4:
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return s->phydata;
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default:
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g_assert_not_reached();
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}
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}
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static void aspeed_mii_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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AspeedMiiState *s = ASPEED_MII(opaque);
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switch (addr) {
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case 0x0:
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s->phycr = value & ~(s->phycr & ASPEED_MII_PHYCR_FIRE);
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break;
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case 0x4:
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s->phydata = value & ~(0xffff | ASPEED_MII_PHYDATA_IDLE);
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break;
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default:
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g_assert_not_reached();
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}
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aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
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aspeed_mii_do_phy_ctl(s);
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}
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static const MemoryRegionOps aspeed_mii_ops = {
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.read = aspeed_mii_read,
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.write = aspeed_mii_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void aspeed_mii_reset(DeviceState *dev)
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{
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AspeedMiiState *s = ASPEED_MII(dev);
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s->phycr = 0;
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s->phydata = 0;
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aspeed_mii_transition(s, !!(s->phycr & ASPEED_MII_PHYCR_FIRE));
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};
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static void aspeed_mii_realize(DeviceState *dev, Error **errp)
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{
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AspeedMiiState *s = ASPEED_MII(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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Object *obj;
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Error *local_err = NULL;
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obj = object_property_get_link(OBJECT(dev), "nic", &local_err);
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if (!obj) {
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error_propagate(errp, local_err);
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error_prepend(errp, "required link 'nic' not found: ");
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return;
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}
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s->nic = FTGMAC100(obj);
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memory_region_init_io(&s->iomem, OBJECT(dev), &aspeed_mii_ops, s,
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TYPE_ASPEED_MII, 0x8);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_aspeed_mii = {
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.name = TYPE_ASPEED_MII,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(phycr, FTGMAC100State),
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VMSTATE_UINT32(phydata, FTGMAC100State),
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VMSTATE_END_OF_LIST()
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}
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};
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static void aspeed_mii_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->vmsd = &vmstate_aspeed_mii;
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dc->reset = aspeed_mii_reset;
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dc->realize = aspeed_mii_realize;
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dc->desc = "Aspeed MII controller";
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}
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static const TypeInfo aspeed_mii_info = {
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.name = TYPE_ASPEED_MII,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedMiiState),
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.class_init = aspeed_mii_class_init,
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};
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static void ftgmac100_register_types(void)
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{
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type_register_static(&ftgmac100_info);
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type_register_static(&aspeed_mii_info);
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}
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type_init(ftgmac100_register_types)
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@ -52,6 +52,7 @@ typedef struct AspeedSoCState {
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AspeedSDMCState sdmc;
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AspeedWDTState wdt[ASPEED_WDTS_NUM];
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FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
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AspeedMiiState mii[ASPEED_MACS_NUM];
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AspeedGPIOState gpio;
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AspeedGPIOState gpio_1_8v;
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AspeedSDHCIState sdhci;
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@ -117,6 +118,10 @@ enum {
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ASPEED_ETH2,
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ASPEED_ETH3,
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ASPEED_ETH4,
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ASPEED_MII1,
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ASPEED_MII2,
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ASPEED_MII3,
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ASPEED_MII4,
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ASPEED_SDRAM,
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ASPEED_XDMA,
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};
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@ -66,4 +66,21 @@ typedef struct FTGMAC100State {
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uint32_t rxdes0_edorr;
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} FTGMAC100State;
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#define TYPE_ASPEED_MII "aspeed-mmi"
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#define ASPEED_MII(obj) OBJECT_CHECK(AspeedMiiState, (obj), TYPE_ASPEED_MII)
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/*
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* AST2600 MII controller
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*/
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typedef struct AspeedMiiState {
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/*< private >*/
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SysBusDevice parent_obj;
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FTGMAC100State *nic;
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MemoryRegion iomem;
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uint32_t phycr;
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uint32_t phydata;
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} AspeedMiiState;
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#endif
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