target/riscv: gdbstub: Minor change for better readability
Use a variable 'base_reg' to represent cs->gdb_num_regs so that the call to ricsv_gen_dynamic_vector_xml() can be placed in one single line for better readability. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230228104035.1879882-5-bmeng@tinylab.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -385,9 +385,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
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32, "riscv-32bit-fpu.xml", 0);
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}
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if (env->misa_ext & RVV) {
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int base_reg = cs->gdb_num_regs;
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gdb_register_coprocessor(cs, riscv_gdb_get_vector, riscv_gdb_set_vector,
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ricsv_gen_dynamic_vector_xml(cs,
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cs->gdb_num_regs),
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ricsv_gen_dynamic_vector_xml(cs, base_reg),
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"riscv-vector.xml", 0);
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}
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switch (env->misa_mxl_max) {
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