target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns
These instructions are part of pool15, see the grand opcode organization tree on top of the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-23-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Siarhei Volkau
Philippe Mathieu-Daudé
parent
968045b6c7
commit
29059e72b0
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@ -290,9 +290,9 @@
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* ├─ 100010 ─ OPC_MXU_S8LDD
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* ├─ 100011 ─ OPC_MXU_S8STD 15..14
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* ├─ 100100 ─ OPC_MXU_S8LDI ┌─ 00 ─ OPC_MXU_S32MUL
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* ├─ 100101 ─ OPC_MXU_S8SDI ├─ 00 ─ OPC_MXU_S32MULU
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* │ ├─ 00 ─ OPC_MXU_S32EXTR
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* ├─ 100110 ─ OPC_MXU__POOL15 ─┴─ 00 ─ OPC_MXU_S32EXTRV
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* ├─ 100101 ─ OPC_MXU_S8SDI ├─ 01 ─ OPC_MXU_S32MULU
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* │ ├─ 10 ─ OPC_MXU_S32EXTR
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* ├─ 100110 ─ OPC_MXU__POOL15 ─┴─ 11 ─ OPC_MXU_S32EXTRV
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* │
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* │ 20..18
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* ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW
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@ -385,6 +385,7 @@ enum {
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OPC_MXU_S8STD = 0x23,
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OPC_MXU_S8LDI = 0x24,
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OPC_MXU_S8SDI = 0x25,
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OPC_MXU__POOL15 = 0x26,
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OPC_MXU__POOL16 = 0x27,
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OPC_MXU__POOL17 = 0x28,
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OPC_MXU_S16LDD = 0x2A,
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@ -477,6 +478,16 @@ enum {
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OPC_MXU_D8SUMC = 0x02,
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};
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/*
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* MXU pool 15
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*/
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enum {
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OPC_MXU_S32MUL = 0x00,
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OPC_MXU_S32MULU = 0x01,
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OPC_MXU_S32EXTR = 0x02,
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OPC_MXU_S32EXTRV = 0x03,
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};
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/*
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* MXU pool 16
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*/
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@ -871,6 +882,47 @@ static void gen_mxu_s16std(DisasContext *ctx, bool postmodify)
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tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_UW);
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}
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/*
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* S32MUL XRa, XRd, rs, rt - Signed 32x32=>64 bit multiplication
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* of GPR's and stores result into pair of MXU registers.
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* It strains HI and LO registers.
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*
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* S32MULU XRa, XRd, rs, rt - Unsigned 32x32=>64 bit multiplication
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* of GPR's and stores result into pair of MXU registers.
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* It strains HI and LO registers.
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*/
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static void gen_mxu_s32mul(DisasContext *ctx, bool mulu)
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{
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TCGv t0, t1;
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uint32_t XRa, XRd, rs, rt;
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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XRa = extract32(ctx->opcode, 6, 4);
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XRd = extract32(ctx->opcode, 10, 4);
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rs = extract32(ctx->opcode, 16, 5);
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rt = extract32(ctx->opcode, 21, 5);
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if (unlikely(rs == 0 || rt == 0)) {
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tcg_gen_movi_tl(t0, 0);
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tcg_gen_movi_tl(t1, 0);
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} else {
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gen_load_gpr(t0, rs);
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gen_load_gpr(t1, rt);
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if (mulu) {
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tcg_gen_mulu2_tl(t0, t1, t0, t1);
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} else {
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tcg_gen_muls2_tl(t0, t1, t0, t1);
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}
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}
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tcg_gen_mov_tl(cpu_HI[0], t1);
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tcg_gen_mov_tl(cpu_LO[0], t0);
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gen_store_mxu_gpr(t1, XRa);
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gen_store_mxu_gpr(t0, XRd);
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}
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/*
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* D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication
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* D16MULF XRa, XRb, XRc, optn2 - Signed Q15 fraction pattern multiplication
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@ -3014,9 +3066,122 @@ static void gen_mxu_d32asum(DisasContext *ctx)
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* MXU instruction category: Miscellaneous
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* Q16SAT
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* S32EXTR
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* S32EXTRV
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* Q16SAT
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*/
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/*
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* S32EXTR XRa, XRd, rs, bits5
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* Extract bits5 bits from 64-bit pair {XRa:XRd}
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* starting from rs[4:0] offset and put to the XRa.
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*/
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static void gen_mxu_s32extr(DisasContext *ctx)
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{
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TCGv t0, t1, t2, t3;
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uint32_t XRa, XRd, rs, bits5;
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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t2 = tcg_temp_new();
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t3 = tcg_temp_new();
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XRa = extract32(ctx->opcode, 6, 4);
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XRd = extract32(ctx->opcode, 10, 4);
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bits5 = extract32(ctx->opcode, 16, 5);
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rs = extract32(ctx->opcode, 21, 5);
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/* {tmp} = {XRa:XRd} >> (64 - rt - bits5); */
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/* {XRa} = extract({tmp}, 0, bits5); */
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if (bits5 > 0) {
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TCGLabel *l_xra_only = gen_new_label();
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TCGLabel *l_done = gen_new_label();
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gen_load_mxu_gpr(t0, XRd);
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gen_load_mxu_gpr(t1, XRa);
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gen_load_gpr(t2, rs);
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tcg_gen_andi_tl(t2, t2, 0x1f);
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tcg_gen_subfi_tl(t2, 32, t2);
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tcg_gen_brcondi_tl(TCG_COND_GE, t2, bits5, l_xra_only);
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tcg_gen_subfi_tl(t2, bits5, t2);
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tcg_gen_subfi_tl(t3, 32, t2);
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tcg_gen_shr_tl(t0, t0, t3);
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tcg_gen_shl_tl(t1, t1, t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_gen_br(l_done);
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gen_set_label(l_xra_only);
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tcg_gen_subi_tl(t2, t2, bits5);
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tcg_gen_shr_tl(t0, t1, t2);
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gen_set_label(l_done);
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tcg_gen_extract_tl(t0, t0, 0, bits5);
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} else {
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/* unspecified behavior but matches tests on real hardware*/
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tcg_gen_movi_tl(t0, 0);
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}
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gen_store_mxu_gpr(t0, XRa);
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}
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/*
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* S32EXTRV XRa, XRd, rs, rt
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* Extract rt[4:0] bits from 64-bit pair {XRa:XRd}
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* starting from rs[4:0] offset and put to the XRa.
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*/
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static void gen_mxu_s32extrv(DisasContext *ctx)
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{
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TCGv t0, t1, t2, t3, t4;
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uint32_t XRa, XRd, rs, rt;
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t0 = tcg_temp_new();
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t1 = tcg_temp_new();
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t2 = tcg_temp_new();
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t3 = tcg_temp_new();
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t4 = tcg_temp_new();
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TCGLabel *l_xra_only = gen_new_label();
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TCGLabel *l_done = gen_new_label();
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TCGLabel *l_zero = gen_new_label();
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TCGLabel *l_extract = gen_new_label();
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XRa = extract32(ctx->opcode, 6, 4);
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XRd = extract32(ctx->opcode, 10, 4);
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rt = extract32(ctx->opcode, 16, 5);
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rs = extract32(ctx->opcode, 21, 5);
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/* {tmp} = {XRa:XRd} >> (64 - rs - rt) */
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gen_load_mxu_gpr(t0, XRd);
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gen_load_mxu_gpr(t1, XRa);
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gen_load_gpr(t2, rs);
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gen_load_gpr(t4, rt);
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tcg_gen_brcondi_tl(TCG_COND_EQ, t4, 0, l_zero);
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tcg_gen_andi_tl(t2, t2, 0x1f);
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tcg_gen_subfi_tl(t2, 32, t2);
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tcg_gen_brcond_tl(TCG_COND_GE, t2, t4, l_xra_only);
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tcg_gen_sub_tl(t2, t4, t2);
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tcg_gen_subfi_tl(t3, 32, t2);
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tcg_gen_shr_tl(t0, t0, t3);
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tcg_gen_shl_tl(t1, t1, t2);
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tcg_gen_or_tl(t0, t0, t1);
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tcg_gen_br(l_extract);
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gen_set_label(l_xra_only);
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tcg_gen_sub_tl(t2, t2, t4);
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tcg_gen_shr_tl(t0, t1, t2);
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tcg_gen_br(l_extract);
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/* unspecified behavior but matches tests on real hardware*/
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gen_set_label(l_zero);
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tcg_gen_movi_tl(t0, 0);
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tcg_gen_br(l_done);
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/* {XRa} = extract({tmp}, 0, rt) */
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gen_set_label(l_extract);
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tcg_gen_subfi_tl(t4, 32, t4);
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tcg_gen_shl_tl(t0, t0, t4);
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tcg_gen_shr_tl(t0, t0, t4);
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gen_set_label(l_done);
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gen_store_mxu_gpr(t0, XRa);
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}
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/*
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* Q16SAT XRa, XRb, XRc
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* Packs four 16-bit signed integers in XRb and XRc to
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@ -3695,6 +3860,30 @@ static void decode_opc_mxu__pool14(DisasContext *ctx)
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}
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}
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static void decode_opc_mxu__pool15(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 14, 2);
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switch (opcode) {
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case OPC_MXU_S32MUL:
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gen_mxu_s32mul(ctx, false);
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break;
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case OPC_MXU_S32MULU:
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gen_mxu_s32mul(ctx, true);
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break;
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case OPC_MXU_S32EXTR:
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gen_mxu_s32extr(ctx);
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break;
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case OPC_MXU_S32EXTRV:
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gen_mxu_s32extrv(ctx);
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break;
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default:
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MIPS_INVAL("decode_opc_mxu");
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gen_reserved_instruction(ctx);
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break;
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}
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}
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static void decode_opc_mxu__pool16(DisasContext *ctx)
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{
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uint32_t opcode = extract32(ctx->opcode, 18, 3);
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@ -3884,6 +4073,9 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
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case OPC_MXU_S8SDI:
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gen_mxu_s8std(ctx, true);
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break;
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case OPC_MXU__POOL15:
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decode_opc_mxu__pool15(ctx);
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break;
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case OPC_MXU__POOL16:
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decode_opc_mxu__pool16(ctx);
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break;
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