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target/ppc: Add E500 L2CSR0 write helper

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Per EREF 2.0 [1] chapter 3.11.2:

The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):

- L2FI  (L2 cache flash invalidate)
- L2FL  (L2 cache flush)
- L2LFC (L2 cache lock flash clear)

when set, a cache operation is initiated by hardware, and these bits
will be cleared when the operation is complete.

Since we don't model cache in QEMU, let's add a write helper to emulate
the cache operations completing instantly.

[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf

Signed-off-by: Bin Meng <bin.meng@windriver.com>

Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bin Meng 2021-02-10 10:45:52 +08:00 committed by David Gibson
parent ce8e43760e
commit 298091f831
2 changed files with 22 additions and 0 deletions
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6
target/ppc/cpu.h
View File

@ -1919,6 +1919,7 @@ typedef PowerPCCPU ArchCPU;
#define SPR_750FX_HID2 (0x3F8)
#define SPR_Exxx_L1FINV0 (0x3F8)
#define SPR_L2CR (0x3F9)
#define SPR_Exxx_L2CSR0 (0x3F9)
#define SPR_L3CR (0x3FA)
#define SPR_750_TDCH (0x3FA)
#define SPR_IABR2 (0x3FA)
@ -1974,6 +1975,11 @@ typedef PowerPCCPU ArchCPU;
#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
/* E500 L2CSR0 */
#define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */
#define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */
#define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */
/* HID0 bits */
#define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
#define HID0_DOZE (1 << 23) /* pre-2.06 */

16
target/ppc/translate_init.c.inc
View File

@ -1735,6 +1735,16 @@ static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
tcg_temp_free(t0);
}
static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn)
{
TCGv t0 = tcg_temp_new();
tcg_gen_andi_tl(t0, cpu_gpr[gprn],
~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC));
gen_store_spr(sprn, t0);
tcg_temp_free(t0);
}
static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
{
gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
@ -5029,6 +5039,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_e500_l1csr1,
0x00000000);
if (version != fsl_e500v1 && version != fsl_e500v2) {
spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_e500_l2csr0,
0x00000000);
}
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,