OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/hppa: Use tcg_constant_*

Browse Source 
Replace uses of tcg_const_* with the allocate and free close together.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-07-08 12:41:29 -07:00
parent e0efc48fbc
commit 29dd6f644a
1 changed files with 18 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
target/hppa/translate.c
View File

@ -144,6 +144,7 @@
#define tcg_gen_sextract_reg tcg_gen_sextract_i64
#define tcg_const_reg tcg_const_i64
#define tcg_const_local_reg tcg_const_local_i64
#define tcg_constant_reg tcg_constant_i64
#define tcg_gen_movcond_reg tcg_gen_movcond_i64
#define tcg_gen_add2_reg tcg_gen_add2_i64
#define tcg_gen_sub2_reg tcg_gen_sub2_i64
@ -238,6 +239,7 @@
#define tcg_gen_sextract_reg tcg_gen_sextract_i32
#define tcg_const_reg tcg_const_i32
#define tcg_const_local_reg tcg_const_local_i32
#define tcg_constant_reg tcg_constant_i32
#define tcg_gen_movcond_reg tcg_gen_movcond_i32
#define tcg_gen_add2_reg tcg_gen_add2_i32
#define tcg_gen_sub2_reg tcg_gen_sub2_i32
@ -771,9 +773,7 @@ static inline target_ureg iaoq_dest(DisasContext *ctx, target_sreg disp)
static void gen_excp_1(int exception)
{
TCGv_i32 t = tcg_const_i32(exception);
gen_helper_excp(cpu_env, t);
tcg_temp_free_i32(t);
gen_helper_excp(cpu_env, tcg_constant_i32(exception));
}
static void gen_excp(DisasContext *ctx, int exception)
@ -787,12 +787,9 @@ static void gen_excp(DisasContext *ctx, int exception)
static bool gen_excp_iir(DisasContext *ctx, int exc)
{
TCGv_reg tmp;
nullify_over(ctx);
tmp = tcg_const_reg(ctx->insn);
tcg_gen_st_reg(tmp, cpu_env, offsetof(CPUHPPAState, cr[CR_IIR]));
tcg_temp_free(tmp);
tcg_gen_st_reg(tcg_constant_reg(ctx->insn),
cpu_env, offsetof(CPUHPPAState, cr[CR_IIR]));
gen_excp(ctx, exc);
return nullify_end(ctx);
}
@ -1150,13 +1147,12 @@ static void do_add(DisasContext *ctx, unsigned rt, TCGv_reg in1,
}
if (!is_l || cond_need_cb(c)) {
TCGv_reg zero = tcg_const_reg(0);
TCGv_reg zero = tcg_constant_reg(0);
cb_msb = get_temp(ctx);
tcg_gen_add2_reg(dest, cb_msb, in1, zero, in2, zero);
if (is_c) {
tcg_gen_add2_reg(dest, cb_msb, dest, cb_msb, cpu_psw_cb_msb, zero);
}
tcg_temp_free(zero);
if (!is_l) {
cb = get_temp(ctx);
tcg_gen_xor_reg(cb, in1, in2);
@ -1242,7 +1238,7 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
cb = tcg_temp_new();
cb_msb = tcg_temp_new();
zero = tcg_const_reg(0);
zero = tcg_constant_reg(0);
if (is_b) {
/* DEST,C = IN1 + ~IN2 + C. */
tcg_gen_not_reg(cb, in2);
@ -1258,7 +1254,6 @@ static void do_sub(DisasContext *ctx, unsigned rt, TCGv_reg in1,
tcg_gen_eqv_reg(cb, in1, in2);
tcg_gen_xor_reg(cb, cb, dest);
}
tcg_temp_free(zero);
/* Compute signed overflow if required. */
sv = NULL;
@ -2449,17 +2444,16 @@ static bool trans_probe(DisasContext *ctx, arg_probe *a)
form_gva(ctx, &addr, &ofs, a->b, 0, 0, 0, a->sp, 0, false);
if (a->imm) {
level = tcg_const_i32(a->ri);
level = tcg_constant_i32(a->ri);
} else {
level = tcg_temp_new_i32();
tcg_gen_trunc_reg_i32(level, load_gpr(ctx, a->ri));
tcg_gen_andi_i32(level, level, 3);
}
want = tcg_const_i32(a->write ? PAGE_WRITE : PAGE_READ);
want = tcg_constant_i32(a->write ? PAGE_WRITE : PAGE_READ);
gen_helper_probe(dest, cpu_env, addr, level, want);
tcg_temp_free_i32(want);
tcg_temp_free_i32(level);
save_gpr(ctx, a->t, dest);
@ -2599,17 +2593,13 @@ static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
static bool trans_lci(DisasContext *ctx, arg_lci *a)
{
TCGv_reg ci;
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
/* The Coherence Index is an implementation-defined function of the
physical address. Two addresses with the same CI have a coherent
view of the cache. Our implementation is to return 0 for all,
since the entire address space is coherent. */
ci = tcg_const_reg(0);
save_gpr(ctx, a->t, ci);
tcg_temp_free(ci);
save_gpr(ctx, a->t, tcg_constant_reg(0));
cond_free(&ctx->null_cond);
return true;
@ -2710,8 +2700,6 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
* currently implemented as idle.
*/
if ((rt == 10 || rt == 31) && r1 == rt && r2 == rt) { /* PAUSE */
TCGv_i32 tmp;
/* No need to check for supervisor, as userland can only pause
until the next timer interrupt. */
nullify_over(ctx);
@ -2722,10 +2710,8 @@ static bool trans_or(DisasContext *ctx, arg_rrr_cf *a)
nullify_set(ctx, 0);
/* Tell the qemu main loop to halt until this cpu has work. */
tmp = tcg_const_i32(1);
tcg_gen_st_i32(tmp, cpu_env, -offsetof(HPPACPU, env) +
offsetof(CPUState, halted));
tcg_temp_free_i32(tmp);
tcg_gen_st_i32(tcg_constant_i32(1), cpu_env,
offsetof(CPUState, halted) - offsetof(HPPACPU, env));
gen_excp_1(EXCP_HALTED);
ctx->base.is_jmp = DISAS_NORETURN;
@ -2833,7 +2819,7 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
add2 = tcg_temp_new();
addc = tcg_temp_new();
dest = tcg_temp_new();
zero = tcg_const_reg(0);
zero = tcg_constant_reg(0);
/* Form R1 << 1 | PSW[CB]{8}. */
tcg_gen_add_reg(add1, in1, in1);
@ -2851,7 +2837,6 @@ static bool trans_ds(DisasContext *ctx, arg_rrr_cf *a)
tcg_gen_add2_i32(dest, cpu_psw_cb_msb, dest, cpu_psw_cb_msb, addc, zero);
tcg_temp_free(addc);
tcg_temp_free(zero);
/* Write back the result register. */
save_gpr(ctx, a->t, dest);
@ -2967,9 +2952,8 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a)
*/
gen_helper_ldc_check(addr);
zero = tcg_const_reg(0);
zero = tcg_constant_reg(0);
tcg_gen_atomic_xchg_reg(dest, addr, zero, ctx->mmu_idx, mop);
tcg_temp_free(zero);
if (a->m) {
save_gpr(ctx, a->b, ofs);
@ -3882,15 +3866,13 @@ static bool trans_fcmp_f(DisasContext *ctx, arg_fclass2 *a)
ta = load_frw0_i32(a->r1);
tb = load_frw0_i32(a->r2);
ty = tcg_const_i32(a->y);
tc = tcg_const_i32(a->c);
ty = tcg_constant_i32(a->y);
tc = tcg_constant_i32(a->c);
gen_helper_fcmp_s(cpu_env, ta, tb, ty, tc);
tcg_temp_free_i32(ta);
tcg_temp_free_i32(tb);
tcg_temp_free_i32(ty);
tcg_temp_free_i32(tc);
return nullify_end(ctx);
}
@ -3904,15 +3886,13 @@ static bool trans_fcmp_d(DisasContext *ctx, arg_fclass2 *a)
ta = load_frd0(a->r1);
tb = load_frd0(a->r2);
ty = tcg_const_i32(a->y);
tc = tcg_const_i32(a->c);
ty = tcg_constant_i32(a->y);
tc = tcg_constant_i32(a->c);
gen_helper_fcmp_d(cpu_env, ta, tb, ty, tc);
tcg_temp_free_i64(ta);
tcg_temp_free_i64(tb);
tcg_temp_free_i32(ty);
tcg_temp_free_i32(tc);
return nullify_end(ctx);
}