[sh4] memory mapped TLB entries
SH4 MMU's memory mapped TLB feature is implemented. SH-Linux seems to write to memory mapped TLB to invalidate a TLB entry, but does not to read it. So only memory write feature is implemented. Work on memory read feature is left. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5067 c046a42c-6fe2-441c-8c8c-71466251a162
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aurel32
parent
274a9e70de
commit
29e179bc3f
110
hw/sh7750.c
110
hw/sh7750.c
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@ -30,6 +30,7 @@
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#include "sh7750_regs.h"
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#include "sh7750_regnames.h"
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#include "sh_intc.h"
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#include "cpu.h"
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#define NB_DEVICES 4
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@ -532,10 +533,113 @@ static struct intc_group groups_pci[] = {
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#define SH_CPU_SH7750_ALL (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7750R)
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#define SH_CPU_SH7751_ALL (SH_CPU_SH7751 | SH_CPU_SH7751R)
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/**********************************************************************
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Memory mapped cache and TLB
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**********************************************************************/
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#define MM_REGION_MASK 0x07000000
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#define MM_ICACHE_ADDR (0)
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#define MM_ICACHE_DATA (1)
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#define MM_ITLB_ADDR (2)
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#define MM_ITLB_DATA (3)
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#define MM_OCACHE_ADDR (4)
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#define MM_OCACHE_DATA (5)
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#define MM_UTLB_ADDR (6)
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#define MM_UTLB_DATA (7)
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#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
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static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
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{
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assert(0);
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return 0;
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}
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static uint32_t sh7750_mmct_readl(void *opaque, target_phys_addr_t addr)
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{
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uint32_t ret = 0;
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switch (MM_REGION_TYPE(addr)) {
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case MM_ICACHE_ADDR:
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case MM_ICACHE_DATA:
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/* do nothing */
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break;
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case MM_ITLB_ADDR:
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case MM_ITLB_DATA:
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/* XXXXX */
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assert(0);
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break;
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case MM_OCACHE_ADDR:
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case MM_OCACHE_DATA:
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/* do nothing */
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break;
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case MM_UTLB_ADDR:
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case MM_UTLB_DATA:
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/* XXXXX */
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assert(0);
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break;
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default:
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assert(0);
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}
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return ret;
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}
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static void invalid_write(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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assert(0);
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}
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static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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SH7750State *s = opaque;
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switch (MM_REGION_TYPE(addr)) {
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case MM_ICACHE_ADDR:
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case MM_ICACHE_DATA:
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/* do nothing */
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break;
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case MM_ITLB_ADDR:
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case MM_ITLB_DATA:
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/* XXXXX */
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assert(0);
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break;
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case MM_OCACHE_ADDR:
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case MM_OCACHE_DATA:
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/* do nothing */
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break;
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case MM_UTLB_ADDR:
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cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value);
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break;
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case MM_UTLB_DATA:
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/* XXXXX */
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assert(0);
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break;
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default:
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assert(0);
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break;
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}
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}
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static CPUReadMemoryFunc *sh7750_mmct_read[] = {
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invalid_read,
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invalid_read,
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sh7750_mmct_readl
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};
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static CPUWriteMemoryFunc *sh7750_mmct_write[] = {
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invalid_write,
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invalid_write,
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sh7750_mmct_writel
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};
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SH7750State *sh7750_init(CPUSH4State * cpu)
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{
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SH7750State *s;
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int sh7750_io_memory;
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int sh7750_mm_cache_and_tlb; /* memory mapped cache and tlb */
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int cpu_model = SH_CPU_SH7751R; /* for now */
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s = qemu_mallocz(sizeof(SH7750State));
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@ -546,6 +650,12 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
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sh7750_mem_write, s);
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cpu_register_physical_memory(0x1c000000, 0x04000000, sh7750_io_memory);
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sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
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sh7750_mmct_read,
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sh7750_mmct_write, s);
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cpu_register_physical_memory(0xf0000000, 0x08000000,
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sh7750_mm_cache_and_tlb);
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sh_intc_init(&s->intc, NR_SOURCES,
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_INTC_ARRAY(mask_registers),
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_INTC_ARRAY(prio_registers));
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@ -124,6 +124,8 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model);
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int cpu_sh4_exec(CPUSH4State * s);
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int cpu_sh4_signal_handler(int host_signum, void *pinfo,
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void *puc);
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void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
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uint32_t mem_value);
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#include "softfloat.h"
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@ -282,6 +282,29 @@ static int find_tlb_entry(CPUState * env, target_ulong address,
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return match;
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}
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static int same_tlb_entry_exists(const tlb_t * haystack, uint8_t nbtlb,
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const tlb_t * needle)
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{
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int i;
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for (i = 0; i < nbtlb; i++)
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if (!memcmp(&haystack[i], needle, sizeof(tlb_t)))
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return 1;
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return 0;
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}
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static void increment_urc(CPUState * env)
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{
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uint8_t urb, urc;
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/* Increment URC */
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urb = ((env->mmucr) >> 18) & 0x3f;
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urc = ((env->mmucr) >> 10) & 0x3f;
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urc++;
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if (urc == urb || urc == UTLB_SIZE - 1)
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urc = 0;
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
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}
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/* Find itlb entry - update itlb from utlb if necessary and asked for
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Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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Update the itlb from utlb if update is not 0
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@ -313,15 +336,8 @@ int find_itlb_entry(CPUState * env, target_ulong address,
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Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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{
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uint8_t urb, urc;
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/* Increment URC */
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urb = ((env->mmucr) >> 18) & 0x3f;
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urc = ((env->mmucr) >> 10) & 0x3f;
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urc++;
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if (urc == urb || urc == UTLB_SIZE - 1)
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urc = 0;
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env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
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/* per utlb access */
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increment_urc(env);
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/* Return entry */
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return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
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@ -407,8 +423,21 @@ int get_physical_address(CPUState * env, target_ulong * physical,
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return (rw & PAGE_WRITE) ? MMU_DTLB_MISS_WRITE :
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MMU_DTLB_MISS_READ;
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}
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/* Mask upper 3 bits */
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*physical = address & 0x1FFFFFFF;
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if (address >= 0x80000000 && address < 0xc0000000) {
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/* Mask upper 3 bits for P1 and P2 areas */
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*physical = address & 0x1fffffff;
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} else if (address >= 0xfc000000) {
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/*
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* Mask upper 3 bits for control registers in P4 area,
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* to unify access to control registers via P0-P3 area.
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* The addresses for cache store queue, TLB address array
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* are not masked.
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*/
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*physical = address & 0x1fffffff;
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} else {
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/* access to cache store queue, or TLB address array. */
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*physical = address;
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}
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*prot = PAGE_READ | PAGE_WRITE;
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return MMU_OK;
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}
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@ -543,4 +572,75 @@ void cpu_load_tlb(CPUState * env)
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entry->tc = (uint8_t)cpu_ptea_tc(env->ptea);
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}
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void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
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uint32_t mem_value)
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{
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int associate = addr & 0x0000080;
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uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
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uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
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uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
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uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
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if (associate) {
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int i;
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tlb_t * utlb_match_entry = NULL;
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int needs_tlb_flush = 0;
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/* search UTLB */
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for (i = 0; i < UTLB_SIZE; i++) {
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tlb_t * entry = &s->utlb[i];
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if (!entry->v)
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continue;
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if (entry->vpn == vpn && entry->asid == asid) {
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if (utlb_match_entry) {
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/* Multiple TLB Exception */
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s->exception_index = 0x140;
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s->tea = addr;
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break;
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}
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if (entry->v && !v)
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needs_tlb_flush = 1;
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entry->v = v;
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entry->d = d;
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utlb_match_entry = entry;
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}
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increment_urc(s); /* per utlb access */
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}
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/* search ITLB */
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for (i = 0; i < ITLB_SIZE; i++) {
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tlb_t * entry = &s->itlb[i];
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if (entry->vpn == vpn && entry->asid == asid) {
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if (entry->v && !v)
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needs_tlb_flush = 1;
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if (utlb_match_entry)
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*entry = *utlb_match_entry;
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else
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entry->v = v;
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break;
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}
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}
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if (needs_tlb_flush)
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tlb_flush_page(s, vpn << 10);
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} else {
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int index = (addr & 0x00003f00) >> 8;
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tlb_t * entry = &s->utlb[index];
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if (entry->v) {
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/* Overwriting valid entry in utlb. */
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target_ulong address = entry->vpn << 10;
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if (!same_tlb_entry_exists(s->itlb, ITLB_SIZE, entry)) {
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tlb_flush_page(s, address);
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}
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}
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entry->asid = asid;
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entry->vpn = vpn;
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entry->d = d;
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entry->v = v;
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increment_urc(s);
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}
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}
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#endif
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