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fixed x86_64 regression

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4586 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2008-05-25 21:01:05 +00:00
parent 90426a4e2d
commit 2a449d1492
1 changed files with 4 additions and 4 deletions
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8
target-i386/translate.c
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@ -1511,15 +1511,15 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
if (is_right) {
if (is_arith) {
gen_exts(ot, cpu_T[0]);
tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], op2 - 1);
tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
} else {
gen_extu(ot, cpu_T[0]);
tcg_gen_shri_tl(cpu_tmp0, cpu_T[0], op2 - 1);
tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
}
} else {
tcg_gen_shli_tl(cpu_tmp0, cpu_T[0], op2 - 1);
tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
}
}
@ -1532,7 +1532,7 @@ static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
/* update eflags if non zero shift */
if (op2 != 0) {
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp0);
tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
if (is_right)
s->cc_op = CC_OP_SARB + ot;