CRIS translator updates
* Improve translation of the X flag (still some corner cases missing). * First shot att P flag support and conditional stores. * Improve the jump logic. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4684 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
bf44333713
commit
2a44f7f173
@ -73,6 +73,7 @@ TCGv cc_op;
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TCGv cc_size;
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TCGv cc_mask;
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TCGv env_btaken;
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TCGv env_btarget;
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TCGv env_pc;
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@ -104,9 +105,16 @@ typedef struct DisasContext {
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int flags_x;
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int clear_x; /* Clear x after this insn? */
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int user; /* user or kernel mode. */
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int cpustate_changed;
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unsigned int tb_flags; /* tb dependent flags. */
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int is_jmp;
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#define JMP_NOJMP 0
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#define JMP_DIRECT 1
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#define JMP_INDIRECT 2
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int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
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uint32_t jmp_pc;
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int delayed_branch;
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struct TranslationBlock *tb;
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@ -207,8 +215,10 @@ static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
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tcg_gen_andi_tl(cpu_PR[r], tn, 3);
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else {
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tcg_gen_mov_tl(cpu_PR[r], tn);
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if (r == PR_PID)
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if (r == PR_PID)
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tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
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else if (r == PR_CCS)
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dc->cpustate_changed = 1;
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}
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}
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@ -610,7 +620,7 @@ static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
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btaken = tcg_temp_new(TCG_TYPE_TL);
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/* Conditional jmp. */
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t_gen_mov_TN_env(btaken, btaken);
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tcg_gen_mov_tl(btaken, env_btaken);
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tcg_gen_mov_tl(env_pc, pc_false);
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tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
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tcg_gen_mov_tl(env_pc, pc_true);
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@ -628,7 +638,7 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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tcg_gen_movi_tl(env_pc, dest);
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tcg_gen_exit_tb((long)tb + n);
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} else {
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tcg_gen_mov_tl(env_pc, cpu_T[0]);
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tcg_gen_movi_tl(env_pc, dest);
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tcg_gen_exit_tb(0);
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}
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}
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@ -648,6 +658,9 @@ static int sign_extend(unsigned int val, unsigned int width)
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static inline void cris_clear_x_flag(DisasContext *dc)
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{
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if (dc->flagx_known && dc->flags_x)
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dc->flags_uptodate = 0;
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dc->flagx_known = 1;
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dc->flags_x = 0;
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}
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@ -715,6 +728,15 @@ static void cris_evaluate_flags(DisasContext *dc)
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}
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break;
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}
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if (dc->flagx_known) {
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if (dc->flags_x)
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tcg_gen_ori_tl(cpu_PR[PR_CCS],
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cpu_PR[PR_CCS], X_FLAG);
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else
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tcg_gen_andi_tl(cpu_PR[PR_CCS],
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cpu_PR[PR_CCS], ~X_FLAG);
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}
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dc->flags_uptodate = 1;
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}
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}
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@ -723,6 +745,11 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
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{
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uint32_t ovl;
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if (!mask) {
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dc->update_cc = 0;
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return;
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}
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/* Check if we need to evaluate the condition codes due to
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CC overlaying. */
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ovl = (dc->cc_mask ^ mask) & ~mask;
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@ -732,11 +759,6 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
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}
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dc->cc_mask = mask;
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dc->update_cc = 1;
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if (mask == 0)
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dc->update_cc = 0;
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else
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dc->flags_uptodate = 0;
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}
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static void cris_update_cc_op(DisasContext *dc, int op, int size)
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@ -942,7 +964,7 @@ static int arith_cc(DisasContext *dc)
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static void gen_tst_cc (DisasContext *dc, int cond)
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{
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int arith_opt;
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int arith_opt, move_opt;
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/* TODO: optimize more condition codes. */
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@ -955,9 +977,10 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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* code is true.
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*/
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arith_opt = arith_cc(dc) && !dc->flags_uptodate;
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move_opt = (dc->cc_op == CC_OP_MOVE) && !dc->flags_uptodate;
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switch (cond) {
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case CC_EQ:
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if (arith_opt) {
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if (arith_opt || move_opt) {
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/* If cc_result is zero, T0 should be
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non-zero otherwise T0 should be zero. */
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int l1;
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@ -975,7 +998,7 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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}
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break;
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case CC_NE:
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if (arith_opt)
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if (arith_opt || move_opt)
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tcg_gen_mov_tl(cpu_T[0], cc_result);
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else {
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cris_evaluate_flags(dc);
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@ -990,8 +1013,7 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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break;
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case CC_CC:
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cris_evaluate_flags(dc);
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tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
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C_FLAG);
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tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
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break;
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case CC_VS:
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@ -1005,9 +1027,17 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
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break;
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case CC_PL:
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if (arith_opt)
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tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
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else {
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if (arith_opt || move_opt) {
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int bits = 31;
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if (dc->cc_size == 1)
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bits = 7;
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else if (dc->cc_size == 2)
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bits = 15;
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tcg_gen_shri_tl(cpu_T[0], cc_result, bits);
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tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
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} else {
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cris_evaluate_flags(dc);
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tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
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N_FLAG);
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@ -1015,9 +1045,15 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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}
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break;
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case CC_MI:
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if (arith_opt) {
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tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
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tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
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if (arith_opt || move_opt) {
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int bits = 31;
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if (dc->cc_size == 1)
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bits = 7;
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else if (dc->cc_size == 2)
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bits = 15;
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tcg_gen_shri_tl(cpu_T[0], cc_result, 31);
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}
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else {
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cris_evaluate_flags(dc);
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@ -1121,28 +1157,46 @@ static void gen_tst_cc (DisasContext *dc, int cond)
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};
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}
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static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
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static void cris_store_direct_jmp(DisasContext *dc)
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{
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/* Store the direct jmp state into the cpu-state. */
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if (dc->jmp == JMP_DIRECT) {
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tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
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tcg_gen_movi_tl(env_btaken, 1);
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}
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}
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static void cris_prepare_cc_branch (DisasContext *dc,
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int offset, int cond)
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{
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/* This helps us re-schedule the micro-code to insns in delay-slots
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before the actual jump. */
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dc->delayed_branch = 2;
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dc->jmp_pc = dc->pc + offset;
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if (cond != CC_A)
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{
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dc->jmp = JMP_INDIRECT;
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gen_tst_cc (dc, cond);
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t_gen_mov_env_TN(btaken, cpu_T[0]);
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} else
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t_gen_mov_env_TN(btaken, tcg_const_tl(1));
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tcg_gen_movi_tl(env_btarget, dc->pc + offset);
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tcg_gen_mov_tl(env_btaken, cpu_T[0]);
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tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
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} else {
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/* Allow chaining. */
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dc->jmp = JMP_DIRECT;
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}
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}
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/* Dynamic jumps, when the dest is in a live reg for example. */
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void cris_prepare_dyn_jmp (DisasContext *dc)
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/* jumps, when the dest is in a live reg for example. Direct should be set
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when the dest addr is constant to allow tb chaining. */
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static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
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{
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/* This helps us re-schedule the micro-code to insns in delay-slots
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before the actual jump. */
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dc->delayed_branch = 2;
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t_gen_mov_env_TN(btaken, tcg_const_tl(1));
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dc->jmp = type;
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if (type == JMP_INDIRECT)
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tcg_gen_movi_tl(env_btaken, 1);
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}
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void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
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@ -1150,6 +1204,11 @@ void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
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{
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int mem_index = cpu_mmu_index(dc->env);
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/* If we get a fault on a delayslot we must keep the jmp state in
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the cpu-state to be able to re-execute the jmp. */
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if (dc->delayed_branch == 1)
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cris_store_direct_jmp(dc);
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if (size == 1) {
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if (sign)
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tcg_gen_qemu_ld8s(dst, addr, mem_index);
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@ -1172,6 +1231,21 @@ void gen_store (DisasContext *dc, TCGv addr, TCGv val,
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{
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int mem_index = cpu_mmu_index(dc->env);
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/* If we get a fault on a delayslot we must keep the jmp state in
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the cpu-state to be able to re-execute the jmp. */
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if (dc->delayed_branch == 1)
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cris_store_direct_jmp(dc);
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/* Conditional writes. We only support the kind were X and P are known
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at translation time. */
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if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
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dc->postinc = 0;
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cris_evaluate_flags(dc);
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tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
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return;
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}
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/* Remember, operands are flipped. CRIS has reversed order. */
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if (size == 1)
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tcg_gen_qemu_st8(val, addr, mem_index);
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@ -1179,6 +1253,11 @@ void gen_store (DisasContext *dc, TCGv addr, TCGv val,
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tcg_gen_qemu_st16(val, addr, mem_index);
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else
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tcg_gen_qemu_st32(val, addr, mem_index);
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if (dc->flagx_known && dc->flags_x) {
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cris_evaluate_flags(dc);
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tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
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}
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}
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static inline void t_gen_sext(TCGv d, TCGv s, int size)
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@ -1352,6 +1431,8 @@ static unsigned int dec_bccq(DisasContext *dc)
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tmp = offset;
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offset = sign_extend(offset, 8);
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DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
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/* op2 holds the condition-code. */
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cris_cc_mask(dc, 0);
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cris_prepare_cc_branch (dc, offset, cond);
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@ -1463,9 +1544,10 @@ static unsigned int dec_asrq(DisasContext *dc)
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DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
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cris_cc_mask(dc, CC_MASK_NZ);
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cris_alu(dc, CC_OP_ASR,
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tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
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cris_alu(dc, CC_OP_MOVE,
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cpu_R[dc->op2],
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cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
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cpu_R[dc->op2], cpu_R[dc->op2], 4);
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return 2;
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}
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static unsigned int dec_lslq(DisasContext *dc)
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@ -1475,9 +1557,11 @@ static unsigned int dec_lslq(DisasContext *dc)
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cris_cc_mask(dc, CC_MASK_NZ);
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cris_alu(dc, CC_OP_LSL,
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tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
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cris_alu(dc, CC_OP_MOVE,
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cpu_R[dc->op2],
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cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
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cpu_R[dc->op2], cpu_R[dc->op2], 4);
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return 2;
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}
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static unsigned int dec_lsrq(DisasContext *dc)
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@ -1487,9 +1571,10 @@ static unsigned int dec_lsrq(DisasContext *dc)
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cris_cc_mask(dc, CC_MASK_NZ);
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cris_alu(dc, CC_OP_LSR,
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tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
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cris_alu(dc, CC_OP_MOVE,
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cpu_R[dc->op2],
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cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
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cpu_R[dc->op2], cpu_R[dc->op2], 4);
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return 2;
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}
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@ -1962,7 +2047,6 @@ static unsigned int dec_setclrf(DisasContext *dc)
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flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
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| EXTRACT_FIELD(dc->ir, 0, 3);
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DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
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if (set && flags == 0) {
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DIS(fprintf (logfile, "nop\n"));
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return 2;
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@ -1975,13 +2059,30 @@ static unsigned int dec_setclrf(DisasContext *dc)
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flags));
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}
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if (set && (flags & X_FLAG)) {
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dc->flagx_known = 1;
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dc->flags_x = X_FLAG;
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} else {
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dc->flagx_known = 0;
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/* User space is not allowed to touch these. Silently ignore. */
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if (dc->tb_flags & U_FLAG) {
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flags &= ~(I_FLAG | U_FLAG);
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}
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if (flags & X_FLAG) {
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dc->flagx_known = 1;
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if (set)
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dc->flags_x = X_FLAG;
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else
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dc->flags_x = 0;
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}
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/* Break the TB if the P flag changes. */
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if (flags & P_FLAG) {
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if ((set && !(dc->tb_flags & P_FLAG))
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|| (!set && (dc->tb_flags & P_FLAG))) {
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tcg_gen_movi_tl(env_pc, dc->pc + 2);
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dc->is_jmp = DISAS_UPDATE;
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dc->cpustate_changed = 1;
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}
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}
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/* Simply decode the flags. */
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cris_evaluate_flags (dc);
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cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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@ -1989,11 +2090,11 @@ static unsigned int dec_setclrf(DisasContext *dc)
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tcg_gen_movi_tl(cc_op, dc->cc_op);
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if (set) {
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if (!dc->user && (flags & U_FLAG)) {
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if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
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/* Enter user mode. */
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t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
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tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
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dc->is_jmp = DISAS_NEXT;
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dc->cpustate_changed = 1;
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}
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tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
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}
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@ -2030,7 +2131,7 @@ static unsigned int dec_move_rp(DisasContext *dc)
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if (dc->op2 == PR_CCS) {
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cris_evaluate_flags(dc);
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t_gen_mov_TN_reg(cpu_T[0], dc->op1);
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if (dc->user) {
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if (dc->tb_flags & U_FLAG) {
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/* User space is not allowed to touch all flags. */
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tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
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tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
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@ -2051,16 +2152,12 @@ static unsigned int dec_move_pr(DisasContext *dc)
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{
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DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
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cris_cc_mask(dc, 0);
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/* Support register 0 is hardwired to zero.
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Treat it specially. */
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if (dc->op2 == 0)
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tcg_gen_movi_tl(cpu_T[1], 0);
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else if (dc->op2 == PR_CCS) {
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||||
if (dc->op2 == PR_CCS)
|
||||
cris_evaluate_flags(dc);
|
||||
t_gen_mov_TN_preg(cpu_T[1], dc->op2);
|
||||
} else
|
||||
t_gen_mov_TN_preg(cpu_T[1], dc->op2);
|
||||
cris_alu(dc, CC_OP_MOVE,
|
||||
|
||||
t_gen_mov_TN_preg(cpu_T[1], dc->op2);
|
||||
cris_alu(dc, CC_OP_MOVE,
|
||||
cpu_R[dc->op1], cpu_R[dc->op1], cpu_T[1],
|
||||
preg_sizes[dc->op2]);
|
||||
return 2;
|
||||
@ -2410,7 +2507,7 @@ static unsigned int dec_move_mp(DisasContext *dc)
|
||||
cris_cc_mask(dc, 0);
|
||||
if (dc->op2 == PR_CCS) {
|
||||
cris_evaluate_flags(dc);
|
||||
if (dc->user) {
|
||||
if (dc->tb_flags & U_FLAG) {
|
||||
/* User space is not allowed to touch all flags. */
|
||||
tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
|
||||
tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
|
||||
@ -2561,7 +2658,7 @@ static unsigned int dec_jump_p(DisasContext *dc)
|
||||
/* rete will often have low bit set to indicate delayslot. */
|
||||
tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
|
||||
cris_cc_mask(dc, 0);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
cris_prepare_jmp(dc, JMP_INDIRECT);
|
||||
return 2;
|
||||
}
|
||||
|
||||
@ -2576,7 +2673,7 @@ static unsigned int dec_jas_r(DisasContext *dc)
|
||||
abort();
|
||||
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
|
||||
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
cris_prepare_jmp(dc, JMP_INDIRECT);
|
||||
return 2;
|
||||
}
|
||||
|
||||
@ -2589,9 +2686,10 @@ static unsigned int dec_jas_im(DisasContext *dc)
|
||||
DIS(fprintf (logfile, "jas 0x%x\n", imm));
|
||||
cris_cc_mask(dc, 0);
|
||||
/* Store the return address in Pd. */
|
||||
tcg_gen_movi_tl(env_btarget, imm);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
|
||||
dc->jmp_pc = imm;
|
||||
cris_prepare_jmp(dc, JMP_DIRECT);
|
||||
return 6;
|
||||
}
|
||||
|
||||
@ -2604,11 +2702,10 @@ static unsigned int dec_jasc_im(DisasContext *dc)
|
||||
DIS(fprintf (logfile, "jasc 0x%x\n", imm));
|
||||
cris_cc_mask(dc, 0);
|
||||
/* Store the return address in Pd. */
|
||||
tcg_gen_movi_tl(cpu_T[0], imm);
|
||||
tcg_gen_mov_tl(env_btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
|
||||
|
||||
dc->jmp_pc = imm;
|
||||
cris_prepare_jmp(dc, JMP_DIRECT);
|
||||
return 6;
|
||||
}
|
||||
|
||||
@ -2617,11 +2714,9 @@ static unsigned int dec_jasc_r(DisasContext *dc)
|
||||
DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
|
||||
cris_cc_mask(dc, 0);
|
||||
/* Store the return address in Pd. */
|
||||
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
|
||||
tcg_gen_mov_tl(env_btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
|
||||
cris_prepare_jmp(dc, JMP_INDIRECT);
|
||||
return 2;
|
||||
}
|
||||
|
||||
@ -2651,12 +2746,11 @@ static unsigned int dec_bas_im(DisasContext *dc)
|
||||
|
||||
DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
|
||||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
|
||||
tcg_gen_mov_tl(env_btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
/* Store the return address in Pd. */
|
||||
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
|
||||
|
||||
dc->jmp_pc = dc->pc + simm;
|
||||
cris_prepare_jmp(dc, JMP_DIRECT);
|
||||
return 6;
|
||||
}
|
||||
|
||||
@ -2667,12 +2761,11 @@ static unsigned int dec_basc_im(DisasContext *dc)
|
||||
|
||||
DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
|
||||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
|
||||
tcg_gen_mov_tl(env_btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
|
||||
t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
/* Store the return address in Pd. */
|
||||
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
|
||||
|
||||
dc->jmp_pc = dc->pc + simm;
|
||||
cris_prepare_jmp(dc, JMP_DIRECT);
|
||||
return 6;
|
||||
}
|
||||
|
||||
@ -2699,8 +2792,7 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
|
||||
break;
|
||||
case 6:
|
||||
/* break. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
||||
t_gen_mov_env_TN(pc, cpu_T[0]);
|
||||
tcg_gen_movi_tl(env_pc, dc->pc);
|
||||
/* Breaks start at 16 in the exception vector. */
|
||||
t_gen_mov_env_TN(trap_vector,
|
||||
tcg_const_tl(dc->op1 + 16));
|
||||
@ -2884,8 +2976,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
|
||||
for(j = 0; j < env->nb_breakpoints; j++) {
|
||||
if (env->breakpoints[j] == dc->pc) {
|
||||
cris_evaluate_flags (dc);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
||||
t_gen_mov_env_TN(pc, cpu_T[0]);
|
||||
tcg_gen_movi_tl(env_pc, dc->pc);
|
||||
t_gen_raise_exception(EXCP_DEBUG);
|
||||
dc->is_jmp = DISAS_UPDATE;
|
||||
}
|
||||
@ -2940,6 +3031,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
||||
struct DisasContext ctx;
|
||||
struct DisasContext *dc = &ctx;
|
||||
uint32_t next_page_start;
|
||||
target_ulong npc;
|
||||
|
||||
if (!logfile)
|
||||
logfile = stderr;
|
||||
@ -2968,18 +3060,24 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
||||
dc->cc_size_uptodate = -1;
|
||||
|
||||
/* Decode TB flags. */
|
||||
dc->user = tb->flags & U_FLAG;
|
||||
dc->tb_flags = tb->flags & (P_FLAG | U_FLAG | X_FLAG);
|
||||
dc->delayed_branch = !!(tb->flags & 7);
|
||||
if (dc->delayed_branch)
|
||||
dc->jmp = JMP_INDIRECT;
|
||||
else
|
||||
dc->jmp = JMP_NOJMP;
|
||||
|
||||
dc->cpustate_changed = 0;
|
||||
|
||||
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
||||
fprintf(logfile,
|
||||
"srch=%d pc=%x %x bt=%x ds=%lld ccs=%x\n"
|
||||
"srch=%d pc=%x %x flg=%llx bt=%x ds=%lld ccs=%x\n"
|
||||
"pid=%x usp=%x\n"
|
||||
"%x.%x.%x.%x\n"
|
||||
"%x.%x.%x.%x\n"
|
||||
"%x.%x.%x.%x\n"
|
||||
"%x.%x.%x.%x\n",
|
||||
search_pc, dc->pc, dc->ppc,
|
||||
search_pc, dc->pc, dc->ppc, tb->flags,
|
||||
env->btarget, tb->flags & 7,
|
||||
env->pregs[PR_CCS],
|
||||
env->pregs[PR_PID], env->pregs[PR_USP],
|
||||
@ -2997,9 +3095,6 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
||||
do
|
||||
{
|
||||
check_breakpoint(env, dc);
|
||||
if (dc->is_jmp == DISAS_JUMP
|
||||
|| dc->is_jmp == DISAS_SWI)
|
||||
goto done;
|
||||
|
||||
if (search_pc) {
|
||||
j = gen_opc_ptr - gen_opc_buf;
|
||||
@ -3034,13 +3129,20 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
||||
actually genereating any host code, the simulator will just
|
||||
loop doing nothing for on this program location. */
|
||||
if (dc->delayed_branch) {
|
||||
t_gen_mov_env_TN(dslot, tcg_const_tl(0));
|
||||
dc->delayed_branch--;
|
||||
if (dc->delayed_branch == 0)
|
||||
{
|
||||
t_gen_cc_jmp(env_btarget,
|
||||
tcg_const_tl(dc->pc));
|
||||
dc->is_jmp = DISAS_JUMP;
|
||||
if (tb->flags & 7)
|
||||
t_gen_mov_env_TN(dslot,
|
||||
tcg_const_tl(0));
|
||||
if (dc->jmp == JMP_DIRECT) {
|
||||
dc->is_jmp = DISAS_NEXT;
|
||||
} else {
|
||||
t_gen_cc_jmp(env_btarget,
|
||||
tcg_const_tl(dc->pc));
|
||||
dc->is_jmp = DISAS_JUMP;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -3051,28 +3153,33 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
||||
} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
|
||||
&& (dc->pc < next_page_start));
|
||||
|
||||
npc = dc->pc;
|
||||
if (dc->jmp == JMP_DIRECT && !dc->delayed_branch)
|
||||
npc = dc->jmp_pc;
|
||||
|
||||
/* Force an update if the per-tb cpu state has changed. */
|
||||
if (dc->is_jmp == DISAS_NEXT
|
||||
&& (dc->cpustate_changed || !dc->flagx_known
|
||||
|| (dc->flags_x != (tb->flags & X_FLAG)))) {
|
||||
dc->is_jmp = DISAS_UPDATE;
|
||||
tcg_gen_movi_tl(env_pc, npc);
|
||||
}
|
||||
/* Broken branch+delayslot sequence. */
|
||||
if (dc->delayed_branch == 1) {
|
||||
/* Set env->dslot to the size of the branch insn. */
|
||||
t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
|
||||
}
|
||||
|
||||
if (!dc->is_jmp) {
|
||||
D(fprintf(logfile, "!jmp pc=%x jmp=%d db=%d\n", dc->pc,
|
||||
dc->is_jmp, dc->delayed_branch));
|
||||
/* T0 and env_pc should hold the new pc. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
||||
tcg_gen_mov_tl(env_pc, cpu_T[0]);
|
||||
cris_store_direct_jmp(dc);
|
||||
}
|
||||
|
||||
cris_evaluate_flags (dc);
|
||||
done:
|
||||
|
||||
if (__builtin_expect(env->singlestep_enabled, 0)) {
|
||||
tcg_gen_movi_tl(env_pc, npc);
|
||||
t_gen_raise_exception(EXCP_DEBUG);
|
||||
} else {
|
||||
switch(dc->is_jmp) {
|
||||
case DISAS_NEXT:
|
||||
gen_goto_tb(dc, 1, dc->pc);
|
||||
gen_goto_tb(dc, 1, npc);
|
||||
break;
|
||||
default:
|
||||
case DISAS_JUMP:
|
||||
@ -3207,7 +3314,9 @@ CPUCRISState *cpu_cris_init (const char *cpu_model)
|
||||
env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
|
||||
offsetof(CPUState, btarget),
|
||||
"btarget");
|
||||
|
||||
env_btaken = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
|
||||
offsetof(CPUState, btaken),
|
||||
"btaken");
|
||||
for (i = 0; i < 16; i++) {
|
||||
cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
|
||||
offsetof(CPUState, regs[i]),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user