omap_gpmc: Support NAND devices
Support accesses to NAND devices, both by mapping them into the GPMC address space, and via the NAND_COMMAND, NAND_ADDRESS and NAND_DATA GPMC registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
parent
9ed3e1b183
commit
2a952feb83
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@ -122,6 +122,7 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
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target_phys_addr_t base, qemu_irq irq);
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void omap_gpmc_reset(struct omap_gpmc_s *s);
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void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem);
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void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand);
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/*
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* Common IRQ numbers for level 1 interrupt handler
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219
hw/omap_gpmc.c
219
hw/omap_gpmc.c
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@ -43,6 +43,8 @@ struct omap_gpmc_s {
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uint32_t config[7];
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MemoryRegion *iomem;
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MemoryRegion container;
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MemoryRegion nandiomem;
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DeviceState *dev;
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} cs_file[8];
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int ecc_cs;
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int ecc_ptr;
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@ -50,11 +52,135 @@ struct omap_gpmc_s {
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ECCState ecc[9];
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};
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#define OMAP_GPMC_8BIT 0
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#define OMAP_GPMC_16BIT 1
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#define OMAP_GPMC_NOR 0
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#define OMAP_GPMC_NAND 2
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static int omap_gpmc_devtype(struct omap_gpmc_cs_file_s *f)
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{
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return (f->config[0] >> 10) & 3;
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}
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static int omap_gpmc_devsize(struct omap_gpmc_cs_file_s *f)
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{
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/* devsize field is really 2 bits but we ignore the high
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* bit to ensure consistent behaviour if the guest sets
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* it (values 2 and 3 are reserved in the TRM)
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*/
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return (f->config[0] >> 12) & 1;
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}
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static void omap_gpmc_int_update(struct omap_gpmc_s *s)
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{
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qemu_set_irq(s->irq, s->irqen & s->irqst);
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}
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/* Access functions for when a NAND-like device is mapped into memory:
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* all addresses in the region behave like accesses to the relevant
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* GPMC_NAND_DATA_i register (which is actually implemented to call these)
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*/
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static uint64_t omap_nand_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
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uint64_t v;
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nand_setpins(f->dev, 0, 0, 0, 1, 0);
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switch (omap_gpmc_devsize(f)) {
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case OMAP_GPMC_8BIT:
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v = nand_getio(f->dev);
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if (size == 1) {
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return v;
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}
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v |= (nand_getio(f->dev) << 8);
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if (size == 2) {
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return v;
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}
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v |= (nand_getio(f->dev) << 16);
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v |= (nand_getio(f->dev) << 24);
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return v;
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case OMAP_GPMC_16BIT:
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v = nand_getio(f->dev);
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if (size == 1) {
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/* 8 bit read from 16 bit device : probably a guest bug */
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return v & 0xff;
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}
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if (size == 2) {
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return v;
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}
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v |= (nand_getio(f->dev) << 16);
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return v;
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default:
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abort();
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}
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}
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static void omap_nand_setio(DeviceState *dev, uint64_t value,
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int nandsize, int size)
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{
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/* Write the specified value to the NAND device, respecting
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* both size of the NAND device and size of the write access.
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*/
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switch (nandsize) {
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case OMAP_GPMC_8BIT:
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switch (size) {
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case 1:
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nand_setio(dev, value & 0xff);
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break;
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case 2:
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nand_setio(dev, value & 0xff);
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nand_setio(dev, (value >> 8) & 0xff);
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break;
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case 4:
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default:
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nand_setio(dev, value & 0xff);
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nand_setio(dev, (value >> 8) & 0xff);
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nand_setio(dev, (value >> 16) & 0xff);
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nand_setio(dev, (value >> 24) & 0xff);
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break;
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}
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case OMAP_GPMC_16BIT:
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switch (size) {
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case 1:
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/* writing to a 16bit device with 8bit access is probably a guest
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* bug; pass the value through anyway.
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*/
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case 2:
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nand_setio(dev, value & 0xffff);
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break;
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case 4:
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default:
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nand_setio(dev, value & 0xffff);
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nand_setio(dev, (value >> 16) & 0xffff);
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break;
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}
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}
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}
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static void omap_nand_write(void *opaque, target_phys_addr_t addr,
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uint64_t value, unsigned size)
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{
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struct omap_gpmc_cs_file_s *f = (struct omap_gpmc_cs_file_s *)opaque;
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nand_setpins(f->dev, 0, 0, 0, 1, 0);
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omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
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}
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static const MemoryRegionOps omap_nand_ops = {
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.read = omap_nand_read,
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.write = omap_nand_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static MemoryRegion *omap_gpmc_cs_memregion(struct omap_gpmc_s *s, int cs)
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{
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/* Return the MemoryRegion* to map/unmap for this chipselect */
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struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NOR) {
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return f->iomem;
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}
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return &f->nandiomem;
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}
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static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
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{
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struct omap_gpmc_cs_file_s *f = &s->cs_file[cs];
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@ -62,7 +188,7 @@ static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
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uint32_t base = f->config[6] & 0x3f;
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uint32_t size;
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if (!f->iomem) {
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if (!f->iomem && !f->dev) {
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return;
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}
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@ -86,7 +212,8 @@ static void omap_gpmc_cs_map(struct omap_gpmc_s *s, int cs)
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* that the same memory becomes accessible at every <i>size</i> bytes
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* starting from <i>base</i>. */
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memory_region_init(&f->container, "omap-gpmc-file", size);
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memory_region_add_subregion(&f->container, 0, f->iomem);
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memory_region_add_subregion(&f->container, 0,
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omap_gpmc_cs_memregion(s, cs));
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memory_region_add_subregion(get_system_memory(), base,
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&f->container);
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}
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@ -98,12 +225,11 @@ static void omap_gpmc_cs_unmap(struct omap_gpmc_s *s, int cs)
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/* Do nothing unless CSVALID */
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return;
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}
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if (!f->iomem) {
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if (!f->iomem && !f->dev) {
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return;
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}
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memory_region_del_subregion(get_system_memory(), &f->container);
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memory_region_del_subregion(&f->container, f->iomem);
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memory_region_del_subregion(&f->container, omap_gpmc_cs_memregion(s, cs));
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memory_region_destroy(&f->container);
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}
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@ -151,6 +277,24 @@ void omap_gpmc_reset(struct omap_gpmc_s *s)
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ecc_reset(&s->ecc[i]);
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}
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static int gpmc_wordaccess_only(target_phys_addr_t addr)
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{
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/* Return true if the register offset is to a register that
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* only permits word width accesses.
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* Non-word accesses are only OK for GPMC_NAND_DATA/ADDRESS/COMMAND
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* for any chipselect.
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*/
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if (addr >= 0x60 && addr <= 0x1d4) {
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int cs = (addr - 0x60) / 0x30;
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addr -= cs * 0x30;
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if (addr >= 0x7c && addr < 0x88) {
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/* GPMC_NAND_COMMAND, GPMC_NAND_ADDRESS, GPMC_NAND_DATA */
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return 0;
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}
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}
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return 1;
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}
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static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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@ -158,7 +302,7 @@ static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
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int cs;
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struct omap_gpmc_cs_file_s *f;
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if (size != 4) {
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if (size != 4 && gpmc_wordaccess_only(addr)) {
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return omap_badwidth_read32(opaque, addr);
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}
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@ -210,7 +354,10 @@ static uint64_t omap_gpmc_read(void *opaque, target_phys_addr_t addr,
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return f->config[5];
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case 0x78: /* GPMC_CONFIG7 */
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return f->config[6];
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case 0x84: /* GPMC_NAND_DATA */
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case 0x84 ... 0x87: /* GPMC_NAND_DATA */
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
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return omap_nand_read(f, 0, size);
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}
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return 0;
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}
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break;
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@ -260,7 +407,7 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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int cs;
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struct omap_gpmc_cs_file_s *f;
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if (size != 4) {
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if (size != 4 && gpmc_wordaccess_only(addr)) {
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return omap_badwidth_write32(opaque, addr, value);
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}
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@ -336,11 +483,23 @@ static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
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omap_gpmc_cs_map(s, cs);
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}
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break;
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case 0x7c: /* GPMC_NAND_COMMAND */
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case 0x80: /* GPMC_NAND_ADDRESS */
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case 0x84: /* GPMC_NAND_DATA */
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case 0x7c ... 0x7f: /* GPMC_NAND_COMMAND */
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
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nand_setpins(f->dev, 1, 0, 0, 1, 0); /* CLE */
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omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
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}
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break;
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case 0x80 ... 0x83: /* GPMC_NAND_ADDRESS */
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
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nand_setpins(f->dev, 0, 1, 0, 1, 0); /* ALE */
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omap_nand_setio(f->dev, value, omap_gpmc_devsize(f), size);
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}
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break;
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case 0x84 ... 0x87: /* GPMC_NAND_DATA */
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if (omap_gpmc_devtype(f) == OMAP_GPMC_NAND) {
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omap_nand_write(f, 0, value, size);
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}
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break;
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default:
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goto bad_reg;
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}
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@ -403,6 +562,7 @@ static const MemoryRegionOps omap_gpmc_ops = {
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struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
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target_phys_addr_t base, qemu_irq irq)
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{
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int cs;
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struct omap_gpmc_s *s = (struct omap_gpmc_s *)
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g_malloc0(sizeof(struct omap_gpmc_s));
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@ -413,6 +573,19 @@ struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu,
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s->revision = cpu_class_omap3(mpu) ? 0x50 : 0x20;
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omap_gpmc_reset(s);
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/* We have to register a different IO memory handler for each
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* chip select region in case a NAND device is mapped there. We
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* make the region the worst-case size of 256MB and rely on the
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* container memory region in cs_map to chop it down to the actual
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* guest-requested size.
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*/
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for (cs = 0; cs < 8; cs++) {
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memory_region_init_io(&s->cs_file[cs].nandiomem,
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&omap_nand_ops,
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&s->cs_file[cs],
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"omap-nand",
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256 * 1024 * 1024);
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}
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return s;
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}
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@ -428,6 +601,28 @@ void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem)
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f = &s->cs_file[cs];
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omap_gpmc_cs_unmap(s, cs);
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f->config[0] &= ~(0xf << 10);
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f->iomem = iomem;
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omap_gpmc_cs_map(s, cs);
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}
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void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand)
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{
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struct omap_gpmc_cs_file_s *f;
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assert(nand);
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if (cs < 0 || cs >= 8) {
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fprintf(stderr, "%s: bad chip-select %i\n", __func__, cs);
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exit(-1);
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}
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f = &s->cs_file[cs];
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omap_gpmc_cs_unmap(s, cs);
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f->config[0] &= ~(0xf << 10);
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f->config[0] |= (OMAP_GPMC_NAND << 10);
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f->dev = nand;
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if (nand_getbuswidth(f->dev) == 16) {
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f->config[0] |= OMAP_GPMC_16BIT << 12;
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}
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omap_gpmc_cs_map(s, cs);
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}
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