target/openrisc: Reduce tlb to a single dimension
While we had defines for *_WAYS, we didn't define more than 1. Reduce the complexity by eliminating this unused dimension. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
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@ -222,10 +222,8 @@ enum {
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/* TLB size */
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/* TLB size */
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enum {
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enum {
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DTLB_WAYS = 1,
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DTLB_SIZE = 64,
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DTLB_SIZE = 64,
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DTLB_MASK = (DTLB_SIZE-1),
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DTLB_MASK = (DTLB_SIZE-1),
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ITLB_WAYS = 1,
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ITLB_SIZE = 64,
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ITLB_SIZE = 64,
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ITLB_MASK = (ITLB_SIZE-1),
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ITLB_MASK = (ITLB_SIZE-1),
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};
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};
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@ -256,8 +254,8 @@ typedef struct OpenRISCTLBEntry {
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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typedef struct CPUOpenRISCTLBContext {
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typedef struct CPUOpenRISCTLBContext {
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OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
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OpenRISCTLBEntry itlb[ITLB_SIZE];
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OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
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OpenRISCTLBEntry dtlb[DTLB_SIZE];
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int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
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int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
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hwaddr *physical,
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hwaddr *physical,
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@ -42,11 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = {
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.minimum_version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext,
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VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0,
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ITLB_WAYS, ITLB_SIZE, 0,
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vmstate_tlb_entry, OpenRISCTLBEntry),
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vmstate_tlb_entry, OpenRISCTLBEntry),
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VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext,
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VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0,
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DTLB_WAYS, DTLB_SIZE, 0,
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vmstate_tlb_entry, OpenRISCTLBEntry),
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vmstate_tlb_entry, OpenRISCTLBEntry),
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VMSTATE_END_OF_LIST()
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VMSTATE_END_OF_LIST()
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}
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}
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@ -43,19 +43,21 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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int vpn = address >> TARGET_PAGE_BITS;
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int vpn = address >> TARGET_PAGE_BITS;
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int idx = vpn & ITLB_MASK;
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int idx = vpn & ITLB_MASK;
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int right = 0;
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int right = 0;
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uint32_t mr = cpu->env.tlb.itlb[idx].mr;
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uint32_t tr = cpu->env.tlb.itlb[idx].tr;
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if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
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if ((mr >> TARGET_PAGE_BITS) != vpn) {
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return TLBRET_NOMATCH;
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return TLBRET_NOMATCH;
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}
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}
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if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) {
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if (!(mr & 1)) {
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return TLBRET_INVALID;
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return TLBRET_INVALID;
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}
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}
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if (supervisor) {
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if (supervisor) {
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if (cpu->env.tlb.itlb[0][idx].tr & SXE) {
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if (tr & SXE) {
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right |= PAGE_EXEC;
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right |= PAGE_EXEC;
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}
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}
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} else {
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} else {
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if (cpu->env.tlb.itlb[0][idx].tr & UXE) {
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if (tr & UXE) {
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right |= PAGE_EXEC;
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right |= PAGE_EXEC;
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}
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}
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}
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}
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@ -63,8 +65,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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return TLBRET_BADADDR;
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return TLBRET_BADADDR;
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}
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}
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*physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) |
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*physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
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(address & (TARGET_PAGE_SIZE-1));
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*prot = right;
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*prot = right;
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return TLBRET_MATCH;
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return TLBRET_MATCH;
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}
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}
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@ -75,25 +76,27 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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int vpn = address >> TARGET_PAGE_BITS;
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int vpn = address >> TARGET_PAGE_BITS;
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int idx = vpn & DTLB_MASK;
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int idx = vpn & DTLB_MASK;
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int right = 0;
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int right = 0;
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uint32_t mr = cpu->env.tlb.dtlb[idx].mr;
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uint32_t tr = cpu->env.tlb.dtlb[idx].tr;
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if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
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if ((mr >> TARGET_PAGE_BITS) != vpn) {
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return TLBRET_NOMATCH;
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return TLBRET_NOMATCH;
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}
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}
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if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) {
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if (!(mr & 1)) {
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return TLBRET_INVALID;
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return TLBRET_INVALID;
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}
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}
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if (supervisor) {
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if (supervisor) {
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if (cpu->env.tlb.dtlb[0][idx].tr & SRE) {
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if (tr & SRE) {
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right |= PAGE_READ;
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right |= PAGE_READ;
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}
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}
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if (cpu->env.tlb.dtlb[0][idx].tr & SWE) {
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if (tr & SWE) {
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right |= PAGE_WRITE;
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right |= PAGE_WRITE;
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}
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}
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} else {
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} else {
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if (cpu->env.tlb.dtlb[0][idx].tr & URE) {
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if (tr & URE) {
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right |= PAGE_READ;
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right |= PAGE_READ;
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}
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}
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if (cpu->env.tlb.dtlb[0][idx].tr & UWE) {
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if (tr & UWE) {
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right |= PAGE_WRITE;
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right |= PAGE_WRITE;
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}
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}
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}
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}
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@ -105,8 +108,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
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return TLBRET_BADADDR;
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return TLBRET_BADADDR;
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}
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}
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*physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) |
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*physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
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(address & (TARGET_PAGE_SIZE-1));
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*prot = right;
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*prot = right;
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return TLBRET_MATCH;
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return TLBRET_MATCH;
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}
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}
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@ -86,14 +86,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
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case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
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case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
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idx = spr - TO_SPR(1, 512);
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idx = spr - TO_SPR(1, 512);
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if (!(rb & 1)) {
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if (!(rb & 1)) {
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tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK);
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tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK);
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}
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}
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env->tlb.dtlb[0][idx].mr = rb;
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env->tlb.dtlb[idx].mr = rb;
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break;
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break;
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case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
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case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
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idx = spr - TO_SPR(1, 640);
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idx = spr - TO_SPR(1, 640);
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env->tlb.dtlb[0][idx].tr = rb;
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env->tlb.dtlb[idx].tr = rb;
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break;
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break;
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case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
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case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
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case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
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case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
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@ -105,14 +105,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
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case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
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case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
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idx = spr - TO_SPR(2, 512);
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idx = spr - TO_SPR(2, 512);
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if (!(rb & 1)) {
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if (!(rb & 1)) {
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tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK);
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tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK);
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}
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}
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env->tlb.itlb[0][idx].mr = rb;
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env->tlb.itlb[idx].mr = rb;
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break;
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break;
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case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
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case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
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idx = spr - TO_SPR(2, 640);
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idx = spr - TO_SPR(2, 640);
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env->tlb.itlb[0][idx].tr = rb;
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env->tlb.itlb[idx].tr = rb;
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break;
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break;
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case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
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case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
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case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
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case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
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@ -244,11 +244,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
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case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
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idx = spr - TO_SPR(1, 512);
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idx = spr - TO_SPR(1, 512);
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return env->tlb.dtlb[0][idx].mr;
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return env->tlb.dtlb[idx].mr;
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case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
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case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
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idx = spr - TO_SPR(1, 640);
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idx = spr - TO_SPR(1, 640);
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return env->tlb.dtlb[0][idx].tr;
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return env->tlb.dtlb[idx].tr;
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case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
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case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
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case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
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case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
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@ -260,11 +260,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
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case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
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idx = spr - TO_SPR(2, 512);
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idx = spr - TO_SPR(2, 512);
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return env->tlb.itlb[0][idx].mr;
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return env->tlb.itlb[idx].mr;
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case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
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case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
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idx = spr - TO_SPR(2, 640);
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idx = spr - TO_SPR(2, 640);
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return env->tlb.itlb[0][idx].tr;
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return env->tlb.itlb[idx].tr;
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case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
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case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
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case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
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case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
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