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aspeed queue: 

* Extra avocado tests using buildroot images
 * Conversion of the I2C model to the registerfield interface
 * Support for the I2C new register interface on AST2600
 * Various I2C enhancements
 * I2C support for the AST1030
 * Improvement of the Aspeed SMC and m25p80 qtest
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Merge tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu into staging

aspeed queue:

* Extra avocado tests using buildroot images
* Conversion of the I2C model to the registerfield interface
* Support for the I2C new register interface on AST2600
* Various I2C enhancements
* I2C support for the AST1030
* Improvement of the Aspeed SMC and m25p80 qtest

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# gpg: Signature made Wed 22 Jun 2022 01:00:38 AM PDT
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B  0B60 51A3 43C7 CFFB ECA1

* tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu:
  hw: m25p80: fixing individual test failure when tests are running in isolation
  aspeed/hace: Add missing newlines to unimp messages
  aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH always
  hw/i2c/aspeed: add DEV_ADDR in old register mode
  hw/i2c/aspeed: rework raise interrupt trace event
  aspeed: Add I2C buses to AST1030 model
  aspeed/i2c: Add ast1030 controller models
  aspeed: i2c: Move regs and helpers to header file
  aspeed: i2c: Add PKT_DONE IRQ to trace
  aspeed: i2c: Add new mode support
  aspeed: i2c: Use reg array instead of individual vars
  aspeed: i2c: Migrate to registerfields API
  hw/registerfields: Add shared fields macros
  test/avocado/machine_aspeed.py: Add an I2C RTC test
  test/avocado/machine_aspeed.py: Add I2C tests to ast2600-evb
  test/avocado/machine_aspeed.py: Add I2C tests to ast2500-evb
  test/avocado/machine_aspeed.py: Add tests using buildroot images
  test/avocado/machine_aspeed.py: Move OpenBMC tests
  aspeed: Remove fake RTC device on ast2500-evb

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-22 07:27:06 -07:00
parent f200ff158d 92a45bde8c
commit 2b049d2c8d
10 changed files with 1100 additions and 383 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
hw/arm/aspeed.c
View File

@ -519,10 +519,6 @@ static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
/* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
TYPE_TMP105, 0x4d);
/* The AST2500 EVB does not have an RTC. Let's pretend that one is
* plugged on the I2C bus header */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
}
static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
@ -1401,6 +1397,18 @@ static void aspeed_minibmc_machine_init(MachineState *machine)
AST1030_INTERNAL_FLASH_SIZE);
}
static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = &bmc->soc;
/* U10 24C08 connects to SDA/SCL Groupt 1 by default */
uint8_t *eeprom_buf = g_malloc0(32 * 1024);
smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
/* U11 LM75 connects to SDA/SCL Group 2 by default */
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
}
static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
void *data)
{
@ -1412,6 +1420,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
amc->hw_strap1 = 0;
amc->hw_strap2 = 0;
mc->init = aspeed_minibmc_machine_init;
amc->i2c_init = ast1030_evb_i2c_init;
mc->default_ram_size = 0;
mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
amc->fmc_model = "sst25vf032b";

18
hw/arm/aspeed_ast10x0.c
View File

@ -114,6 +114,9 @@ static void aspeed_soc_ast1030_init(Object *obj)
object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
object_initialize_child(obj, "i2c", &s->i2c, typename);
snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
@ -188,6 +191,21 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
/* I2C */
object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
&error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
sc->irqmap[ASPEED_DEV_I2C] + i);
/* The AST1030 I2C controller has one IRQ per bus. */
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
}
/* LPC */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
return;

828
hw/i2c/aspeed_i2c.c
View File

File diff suppressed because it is too large Load Diff

2
hw/i2c/trace-events
View File

@ -9,7 +9,7 @@ i2c_recv(uint8_t address, uint8_t data) "recv(addr:0x%02x) data:0x%02x"
# aspeed_i2c.c
aspeed_i2c_bus_cmd(uint32_t cmd, const char *cmd_flags, uint32_t count, uint32_t intr_status) "handling cmd=0x%x %s count=%d intr=0x%x"
aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char *str1, const char *str2, const char *str3, const char *str4, const char *str5) "handled intr=0x%x %s%s%s%s%s"
aspeed_i2c_bus_raise_interrupt(uint32_t intr_status, const char *s) "handled intr=0x%x %s"
aspeed_i2c_bus_read(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64
aspeed_i2c_bus_write(uint32_t busid, uint64_t offset, unsigned size, uint64_t value) "bus[%d]: To 0x%" PRIx64 " of size %u: 0x%" PRIx64
aspeed_i2c_bus_send(const char *mode, int i, int count, uint8_t byte) "%s send %d/%d 0x%02x"

4
hw/misc/aspeed_hace.c
View File

@ -340,12 +340,12 @@ static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data,
if ((data & HASH_HMAC_MASK)) {
qemu_log_mask(LOG_UNIMP,
"%s: HMAC engine command mode %"PRIx64" not implemented",
"%s: HMAC engine command mode %"PRIx64" not implemented\n",
__func__, (data & HASH_HMAC_MASK) >> 8);
}
if (data & BIT(1)) {
qemu_log_mask(LOG_UNIMP,
"%s: Cascaded mode not implemented",
"%s: Cascaded mode not implemented\n",
__func__);
}
algo = hash_algo_lookup(data);

289
include/hw/i2c/aspeed_i2c.h
View File

@ -23,16 +23,196 @@
#include "hw/i2c/i2c.h"
#include "hw/sysbus.h"
#include "hw/registerfields.h"
#include "qom/object.h"
#define TYPE_ASPEED_I2C "aspeed.i2c"
#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
#define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030"
OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C)
#define ASPEED_I2C_NR_BUSSES 16
#define ASPEED_I2C_MAX_POOL_SIZE 0x800
#define ASPEED_I2C_OLD_NUM_REG 11
#define ASPEED_I2C_NEW_NUM_REG 22
/* Tx State Machine */
#define I2CD_TX_STATE_MASK 0xf
#define I2CD_IDLE 0x0
#define I2CD_MACTIVE 0x8
#define I2CD_MSTART 0x9
#define I2CD_MSTARTR 0xa
#define I2CD_MSTOP 0xb
#define I2CD_MTXD 0xc
#define I2CD_MRXACK 0xd
#define I2CD_MRXD 0xe
#define I2CD_MTXACK 0xf
#define I2CD_SWAIT 0x1
#define I2CD_SRXD 0x4
#define I2CD_STXACK 0x5
#define I2CD_STXD 0x6
#define I2CD_SRXACK 0x7
#define I2CD_RECOVER 0x3
/* I2C Global Register */
REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */
REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */
REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */
FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1)
FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1)
REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */
/* I2C Old Mode Device (Bus) Register */
REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */
FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */
SHARED_FIELD(M_SDA_LOCK_EN, 16, 1)
SHARED_FIELD(MULTI_MASTER_DIS, 15, 1)
SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1)
SHARED_FIELD(MSB_STS, 9, 1)
SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1)
SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1)
SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1)
SHARED_FIELD(DEF_ADDR_EN, 5, 1)
SHARED_FIELD(DEF_ALERT_EN, 4, 1)
SHARED_FIELD(DEF_ARP_EN, 3, 1)
SHARED_FIELD(DEF_GCALL_EN, 2, 1)
SHARED_FIELD(SLAVE_EN, 1, 1)
SHARED_FIELD(MASTER_EN, 0, 1)
REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */
REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */
REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */
REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */
SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */
SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1)
SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1)
SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1)
SHARED_FIELD(BUS_RECOVER_DONE, 13, 1)
SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */
FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */
FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */
FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */
FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */
FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */
SHARED_FIELD(SCL_TIMEOUT, 6, 1)
SHARED_FIELD(ABNORMAL, 5, 1)
SHARED_FIELD(NORMAL_STOP, 4, 1)
SHARED_FIELD(ARBIT_LOSS, 3, 1)
SHARED_FIELD(RX_DONE, 2, 1)
SHARED_FIELD(TX_NAK, 1, 1)
SHARED_FIELD(TX_ACK, 0, 1)
REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */
SHARED_FIELD(SDA_OE, 28, 1)
SHARED_FIELD(SDA_O, 27, 1)
SHARED_FIELD(SCL_OE, 26, 1)
SHARED_FIELD(SCL_O, 25, 1)
SHARED_FIELD(TX_TIMING, 23, 2)
SHARED_FIELD(TX_STATE, 19, 4)
SHARED_FIELD(SCL_LINE_STS, 18, 1)
SHARED_FIELD(SDA_LINE_STS, 17, 1)
SHARED_FIELD(BUS_BUSY_STS, 16, 1)
SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1)
SHARED_FIELD(SDA_O_OUT_DIR, 14, 1)
SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1)
SHARED_FIELD(SCL_O_OUT_DIR, 12, 1)
SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1)
SHARED_FIELD(S_ALT_EN, 10, 1)
/* Command Bits */
SHARED_FIELD(RX_DMA_EN, 9, 1)
SHARED_FIELD(TX_DMA_EN, 8, 1)
SHARED_FIELD(RX_BUFF_EN, 7, 1)
SHARED_FIELD(TX_BUFF_EN, 6, 1)
SHARED_FIELD(M_STOP_CMD, 5, 1)
SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1)
SHARED_FIELD(M_RX_CMD, 3, 1)
SHARED_FIELD(S_TX_CMD, 2, 1)
SHARED_FIELD(M_TX_CMD, 1, 1)
SHARED_FIELD(M_START_CMD, 0, 1)
REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */
REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */
SHARED_FIELD(RX_COUNT, 24, 5)
SHARED_FIELD(RX_SIZE, 16, 5)
SHARED_FIELD(TX_COUNT, 9, 5)
FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */
REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */
SHARED_FIELD(RX_BUF, 8, 8)
SHARED_FIELD(TX_BUF, 0, 8)
REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */
REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */
/* I2C New Mode Device (Bus) Register */
REG32(I2CC_FUN_CTRL, 0x0)
FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1)
FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1)
FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1)
FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2)
/* 17:0 shared with I2CD_FUN_CTRL[17:0] */
REG32(I2CC_AC_TIMING, 0x04)
REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08)
/* 31:16 shared with I2CD_CMD[31:16] */
/* 15:0 shared with I2CD_BYTE_BUF[15:0] */
REG32(I2CC_POOL_CTRL, 0x0c)
/* 31:0 shared with I2CD_POOL_CTRL[31:0] */
REG32(I2CM_INTR_CTRL, 0x10)
REG32(I2CM_INTR_STS, 0x14)
FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4)
FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1)
FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1)
FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1)
FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1)
/* 14:0 shared with I2CD_INTR_STS[14:0] */
REG32(I2CM_CMD, 0x18)
FIELD(I2CM_CMD, W1_CTRL, 31, 1)
FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7)
FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3)
FIELD(I2CM_CMD, PKT_OP_EN, 16, 1)
/* 15:0 shared with I2CD_CMD[15:0] */
REG32(I2CM_DMA_LEN, 0x1c)
FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1)
FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11)
FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)
FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11)
REG32(I2CS_INTR_CTRL, 0x20)
REG32(I2CS_INTR_STS, 0x24)
/* 31:29 shared with I2CD_INTR_STS[31:29] */
FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2)
FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1)
FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1)
FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1)
FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2)
FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1)
FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1)
/* 14:0 shared with I2CD_INTR_STS[14:0] */
REG32(I2CS_CMD, 0x28)
FIELD(I2CS_CMD, W1_CTRL, 31, 1)
FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2)
FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1)
FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1)
FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1)
/* 13:0 shared with I2CD_CMD[13:0] */
REG32(I2CS_DMA_LEN, 0x2c)
FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1)
FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11)
FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1)
FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11)
REG32(I2CM_DMA_TX_ADDR, 0x30)
FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31)
REG32(I2CM_DMA_RX_ADDR, 0x34)
FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31)
REG32(I2CS_DMA_TX_ADDR, 0x38)
FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31)
REG32(I2CS_DMA_RX_ADDR, 0x3c)
FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31)
REG32(I2CS_DEV_ADDR, 0x40)
REG32(I2CM_DMA_LEN_STS, 0x48)
FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13)
FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13)
REG32(I2CS_DMA_LEN_STS, 0x4c)
FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13)
FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13)
REG32(I2CC_DMA_ADDR, 0x50)
REG32(I2CC_DMA_LEN, 0x54)
struct AspeedI2CState;
@ -49,15 +229,7 @@ struct AspeedI2CBus {
uint8_t id;
qemu_irq irq;
uint32_t ctrl;
uint32_t timing[2];
uint32_t intr_ctrl;
uint32_t intr_status;
uint32_t cmd;
uint32_t buf;
uint32_t pool_ctrl;
uint32_t dma_addr;
uint32_t dma_len;
uint32_t regs[ASPEED_I2C_NEW_NUM_REG];
};
struct AspeedI2CState {
@ -68,6 +240,7 @@ struct AspeedI2CState {
uint32_t intr_status;
uint32_t ctrl_global;
uint32_t new_clk_divider;
MemoryRegion pool_iomem;
uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
@ -93,6 +266,104 @@ struct AspeedI2CClass {
};
static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s)
{
return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE);
}
static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN);
}
return false;
}
static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CC_FUN_CTRL;
}
return R_I2CD_FUN_CTRL;
}
static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CM_CMD;
}
return R_I2CD_CMD;
}
static inline uint32_t aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CS_DEV_ADDR;
}
return R_I2CD_DEV_ADDR;
}
static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CM_INTR_CTRL;
}
return R_I2CD_INTR_CTRL;
}
static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CM_INTR_STS;
}
return R_I2CD_INTR_STS;
}
static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CC_POOL_CTRL;
}
return R_I2CD_POOL_CTRL;
}
static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CC_MS_TXRX_BYTE_BUF;
}
return R_I2CD_BYTE_BUF;
}
static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CC_DMA_LEN;
}
return R_I2CD_DMA_LEN;
}
static inline uint32_t aspeed_i2c_bus_dma_addr_offset(AspeedI2CBus *bus)
{
if (aspeed_i2c_is_new_mode(bus->controller)) {
return R_I2CC_DMA_ADDR;
}
return R_I2CD_DMA_ADDR;
}
static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus)
{
return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus),
MASTER_EN);
}
static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus)
{
uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus);
return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) ||
SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN);
}
I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr);
#endif /* ASPEED_I2C_H */

70
include/hw/registerfields.h
View File

@ -154,4 +154,74 @@
#define ARRAY_FIELD_DP64(regs, reg, field, val) \
(regs)[R_ ## reg] = FIELD_DP64((regs)[R_ ## reg], reg, field, val);
/*
* These macros can be used for defining and extracting fields that have the
* same bit position across multiple registers.
*/
/* Define shared SHIFT, LENGTH, and MASK constants */
#define SHARED_FIELD(name, shift, length) \
enum { name ## _ ## SHIFT = (shift)}; \
enum { name ## _ ## LENGTH = (length)}; \
enum { name ## _ ## MASK = MAKE_64BIT_MASK(shift, length)};
/* Extract a shared field */
#define SHARED_FIELD_EX8(storage, field) \
extract8((storage), field ## _SHIFT, field ## _LENGTH)
#define SHARED_FIELD_EX16(storage, field) \
extract16((storage), field ## _SHIFT, field ## _LENGTH)
#define SHARED_FIELD_EX32(storage, field) \
extract32((storage), field ## _SHIFT, field ## _LENGTH)
#define SHARED_FIELD_EX64(storage, field) \
extract64((storage), field ## _SHIFT, field ## _LENGTH)
/* Extract a shared field from a register array */
#define SHARED_ARRAY_FIELD_EX32(regs, offset, field) \
SHARED_FIELD_EX32((regs)[(offset)], field)
#define SHARED_ARRAY_FIELD_EX64(regs, offset, field) \
SHARED_FIELD_EX64((regs)[(offset)], field)
/* Deposit a shared field */
#define SHARED_FIELD_DP8(storage, field, val) ({ \
struct { \
unsigned int v:field ## _LENGTH; \
} _v = { .v = val }; \
uint8_t _d; \
_d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
_d; })
#define SHARED_FIELD_DP16(storage, field, val) ({ \
struct { \
unsigned int v:field ## _LENGTH; \
} _v = { .v = val }; \
uint16_t _d; \
_d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
_d; })
#define SHARED_FIELD_DP32(storage, field, val) ({ \
struct { \
unsigned int v:field ## _LENGTH; \
} _v = { .v = val }; \
uint32_t _d; \
_d = deposit32((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
_d; })
#define SHARED_FIELD_DP64(storage, field, val) ({ \
struct { \
uint64_t v:field ## _LENGTH; \
} _v = { .v = val }; \
uint64_t _d; \
_d = deposit64((storage), field ## _SHIFT, field ## _LENGTH, _v.v); \
_d; })
/* Deposit a shared field to a register array */
#define SHARED_ARRAY_FIELD_DP32(regs, offset, field, val) \
(regs)[(offset)] = SHARED_FIELD_DP32((regs)[(offset)], field, val);
#define SHARED_ARRAY_FIELD_DP64(regs, offset, field, val) \
(regs)[(offset)] = SHARED_FIELD_DP64((regs)[(offset)], field, val);
#endif

43
tests/avocado/boot_linux_console.py
View File

@ -1043,49 +1043,6 @@ class BootLinuxConsole(LinuxKernelTest):
self.vm.add_args('-dtb', self.workdir + '/day16/vexpress-v2p-ca9.dtb')
self.do_test_advcal_2018('16', tar_hash, 'winter.zImage')
def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:palmetto-bmc
"""
image_url = ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
'obmc-phosphor-image-palmetto.static.mtd')
image_hash = ('3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
self.do_test_arm_aspeed(image_path)
def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:romulus-bmc
"""
image_url = ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
'obmc-phosphor-image-romulus.static.mtd')
image_hash = ('820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
self.do_test_arm_aspeed(image_path)
def do_test_arm_aspeed(self, image):
self.vm.set_console()
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
'-net', 'nic')
self.vm.launch()
self.wait_for_console_pattern("U-Boot 2016.07")
self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000")
self.wait_for_console_pattern("Starting kernel ...")
self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")
self.wait_for_console_pattern(
"aspeed-smc 1e620000.spi: read control register: 203b0641")
self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
self.wait_for_console_pattern("systemd[1]: Set hostname to")
def test_arm_ast2600_debian(self):
"""
:avocado: tags=arch:arm

136
tests/avocado/machine_aspeed.py
View File

@ -5,8 +5,11 @@
# This work is licensed under the terms of the GNU GPL, version 2 or
# later. See the COPYING file in the top-level directory.
import time
from avocado_qemu import QemuSystemTest
from avocado_qemu import wait_for_console_pattern
from avocado_qemu import exec_command
from avocado_qemu import exec_command_and_wait_for_pattern
from avocado.utils import archive
@ -34,3 +37,136 @@ class AST1030Machine(QemuSystemTest):
wait_for_console_pattern(self, "Booting Zephyr OS")
exec_command_and_wait_for_pattern(self, "help",
"Available commands")
class AST2x00Machine(QemuSystemTest):
def wait_for_console_pattern(self, success_message, vm=None):
wait_for_console_pattern(self, success_message,
failure_message='Kernel panic - not syncing',
vm=vm)
def do_test_arm_aspeed(self, image):
self.vm.set_console()
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
'-net', 'nic')
self.vm.launch()
self.wait_for_console_pattern("U-Boot 2016.07")
self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000")
self.wait_for_console_pattern("Starting kernel ...")
self.wait_for_console_pattern("Booting Linux on physical CPU 0x0")
wait_for_console_pattern(self,
"aspeed-smc 1e620000.spi: read control register: 203b0641")
self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ")
self.wait_for_console_pattern("systemd[1]: Set hostname to")
def test_arm_ast2400_palmetto_openbmc_v2_9_0(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:palmetto-bmc
"""
image_url = ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
'obmc-phosphor-image-palmetto.static.mtd')
image_hash = ('3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
self.do_test_arm_aspeed(image_path)
def test_arm_ast2500_romulus_openbmc_v2_9_0(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:romulus-bmc
"""
image_url = ('https://github.com/openbmc/openbmc/releases/download/2.9.0/'
'obmc-phosphor-image-romulus.static.mtd')
image_hash = ('820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
self.do_test_arm_aspeed(image_path)
def do_test_arm_aspeed_buidroot_start(self, image, cpu_id):
self.vm.set_console()
self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
'-net', 'nic', '-net', 'user')
self.vm.launch()
self.wait_for_console_pattern('U-Boot 2019.04')
self.wait_for_console_pattern('## Loading kernel from FIT Image')
self.wait_for_console_pattern('Starting kernel ...')
self.wait_for_console_pattern('Booting Linux on physical CPU ' + cpu_id)
self.wait_for_console_pattern('lease of 10.0.2.15')
self.wait_for_console_pattern('Aspeed EVB')
exec_command(self, 'root')
time.sleep(0.1)
def do_test_arm_aspeed_buidroot_poweroff(self):
exec_command_and_wait_for_pattern(self, 'poweroff',
'reboot: System halted');
def test_arm_ast2500_evb_builroot(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:ast2500-evb
"""
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
'images/ast2500-evb/buildroot-2022.05/flash.img')
image_hash = ('549db6e9d8cdaf4367af21c36385a68bb465779c18b5e37094fc7343decccd3f')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
self.vm.add_args('-device',
'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
self.do_test_arm_aspeed_buidroot_start(image_path, '0x0')
exec_command_and_wait_for_pattern(self,
'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
exec_command_and_wait_for_pattern(self,
'cat /sys/class/hwmon/hwmon1/temp1_input', '0')
self.vm.command('qom-set', path='/machine/peripheral/tmp-test',
property='temperature', value=18000);
exec_command_and_wait_for_pattern(self,
'cat /sys/class/hwmon/hwmon1/temp1_input', '18000')
self.do_test_arm_aspeed_buidroot_poweroff()
def test_arm_ast2600_evb_builroot(self):
"""
:avocado: tags=arch:arm
:avocado: tags=machine:ast2600-evb
"""
image_url = ('https://github.com/legoater/qemu-aspeed-boot/raw/master/'
'images/ast2600-evb/buildroot-2022.05/flash.img')
image_hash = ('6cc9e7d128fd4fa1fd01c883af67593cae8072c3239a0b8b6ace857f3538a92d')
image_path = self.fetch_asset(image_url, asset_hash=image_hash,
algorithm='sha256')
self.vm.add_args('-device',
'tmp105,bus=aspeed.i2c.bus.3,address=0x4d,id=tmp-test');
self.vm.add_args('-device',
'ds1338,bus=aspeed.i2c.bus.3,address=0x32');
self.do_test_arm_aspeed_buidroot_start(image_path, '0xf00')
exec_command_and_wait_for_pattern(self,
'echo lm75 0x4d > /sys/class/i2c-dev/i2c-3/device/new_device',
'i2c i2c-3: new_device: Instantiated device lm75 at 0x4d');
exec_command_and_wait_for_pattern(self,
'cat /sys/class/hwmon/hwmon0/temp1_input', '0')
self.vm.command('qom-set', path='/machine/peripheral/tmp-test',
property='temperature', value=18000);
exec_command_and_wait_for_pattern(self,
'cat /sys/class/hwmon/hwmon0/temp1_input', '18000')
exec_command_and_wait_for_pattern(self,
'echo ds1307 0x32 > /sys/class/i2c-dev/i2c-3/device/new_device',
'i2c i2c-3: new_device: Instantiated device ds1307 at 0x32');
year = time.strftime("%Y")
exec_command_and_wait_for_pattern(self, 'hwclock -f /dev/rtc1', year);
self.do_test_arm_aspeed_buidroot_poweroff()

76
tests/qtest/aspeed_smc-test.c
View File

@ -135,6 +135,9 @@ static void flash_reset(void)
spi_ctrl_start_user();
writeb(ASPEED_FLASH_BASE, RESET_ENABLE);
writeb(ASPEED_FLASH_BASE, RESET_MEMORY);
writeb(ASPEED_FLASH_BASE, WREN);
writeb(ASPEED_FLASH_BASE, BULK_ERASE);
writeb(ASPEED_FLASH_BASE, WRDI);
spi_ctrl_stop_user();
spi_conf_remove(CONF_ENABLE_W0);
@ -195,6 +198,33 @@ static void test_erase_sector(void)
spi_conf(CONF_ENABLE_W0);
/*
* Previous page should be full of 0xffs after backend is
* initialized
*/
read_page(some_page_addr - FLASH_PAGE_SIZE, page);
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0xffffffff);
}
spi_ctrl_start_user();
writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
writeb(ASPEED_FLASH_BASE, WREN);
writeb(ASPEED_FLASH_BASE, PP);
writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
/* Fill the page with its own addresses */
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
}
spi_ctrl_stop_user();
/* Check the page is correctly written */
read_page(some_page_addr, page);
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
}
spi_ctrl_start_user();
writeb(ASPEED_FLASH_BASE, WREN);
writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
@ -202,14 +232,7 @@ static void test_erase_sector(void)
writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
spi_ctrl_stop_user();
/* Previous page should be full of zeroes as backend is not
* initialized */
read_page(some_page_addr - FLASH_PAGE_SIZE, page);
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0x0);
}
/* But this one was erased */
/* Check the page is erased */
read_page(some_page_addr, page);
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0xffffffff);
@ -226,11 +249,31 @@ static void test_erase_all(void)
spi_conf(CONF_ENABLE_W0);
/* Check some random page. Should be full of zeroes as backend is
* not initialized */
/*
* Previous page should be full of 0xffs after backend is
* initialized
*/
read_page(some_page_addr - FLASH_PAGE_SIZE, page);
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0xffffffff);
}
spi_ctrl_start_user();
writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
writeb(ASPEED_FLASH_BASE, WREN);
writeb(ASPEED_FLASH_BASE, PP);
writel(ASPEED_FLASH_BASE, make_be32(some_page_addr));
/* Fill the page with its own addresses */
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
writel(ASPEED_FLASH_BASE, make_be32(some_page_addr + i * 4));
}
spi_ctrl_stop_user();
/* Check the page is correctly written */
read_page(some_page_addr, page);
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0x0);
g_assert_cmphex(page[i], ==, some_page_addr + i * 4);
}
spi_ctrl_start_user();
@ -238,7 +281,7 @@ static void test_erase_all(void)
writeb(ASPEED_FLASH_BASE, BULK_ERASE);
spi_ctrl_stop_user();
/* Recheck that some random page */
/* Check the page is erased */
read_page(some_page_addr, page);
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
g_assert_cmphex(page[i], ==, 0xffffffff);
@ -299,6 +342,14 @@ static void test_read_page_mem(void)
spi_conf(CONF_ENABLE_W0);
spi_ctrl_start_user();
writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR);
writeb(ASPEED_FLASH_BASE, WREN);
writeb(ASPEED_FLASH_BASE, PP);
writel(ASPEED_FLASH_BASE, make_be32(my_page_addr));
/* Fill the page with its own addresses */
for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) {
writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4));
}
spi_ctrl_stop_user();
spi_conf_remove(CONF_ENABLE_W0);
@ -417,6 +468,7 @@ int main(int argc, char **argv)
qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
flash_reset();
ret = g_test_run();
qtest_quit(global_qtest);