target/ppc: added ifdefs around TCG-only code
excp_helper.c, mmu-hash64.c and mmu_helper.c have some function declarations that are TCG-only, and couldn't be easily moved to a TCG only file, so ifdefs were added around them. We also needed ifdefs around some header files because helper-proto.h includes trace/generated-helpers.h, which is never created when building without TCG, and cpu_ldst.h includes tcg/tcg.h, whose containing folder is not included as a -iquote. As future cleanup, we could change the part of the configuration script to add those. cpu_init.c also had a callback definition that is TCG only and could be removed as part of a future cleanup (all the dump_statistics part is almost never used and will become obsolete as we transition to using decodetree). Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Message-Id: <20210525115355.8254-3-bruno.larsen@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bruno Larsen (billionai)
David Gibson
parent
52e9612ee9
commit
2b44e21949
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@ -9307,7 +9307,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
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cc->class_by_name = ppc_cpu_class_by_name;
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cc->has_work = ppc_cpu_has_work;
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cc->dump_state = ppc_cpu_dump_state;
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#ifdef CONFIG_TCG
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cc->dump_statistics = ppc_cpu_dump_statistics;
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#endif
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cc->set_pc = ppc_cpu_set_pc;
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cc->gdb_read_register = ppc_cpu_gdb_read_register;
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cc->gdb_write_register = ppc_cpu_gdb_write_register;
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@ -19,12 +19,15 @@
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "internal.h"
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#include "helper_regs.h"
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#ifdef CONFIG_TCG
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#endif
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/* #define DEBUG_OP */
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/* #define DEBUG_SOFTWARE_TLB */
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/* #define DEBUG_EXCEPTIONS */
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@ -1208,6 +1211,7 @@ void raise_exception_ra(CPUPPCState *env, uint32_t exception,
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raise_exception_err_ra(env, exception, 0, raddr);
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}
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#ifdef CONFIG_TCG
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void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
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uint32_t error_code)
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{
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@ -1218,8 +1222,10 @@ void helper_raise_exception(CPUPPCState *env, uint32_t exception)
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{
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raise_exception_err_ra(env, exception, 0, 0);
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}
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#endif
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#if !defined(CONFIG_USER_ONLY)
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#ifdef CONFIG_TCG
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void helper_store_msr(CPUPPCState *env, target_ulong val)
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{
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uint32_t excp = hreg_store_msr(env, val, 0);
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@ -1259,6 +1265,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
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(env->spr[SPR_PSSCR] & PSSCR_EC);
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}
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#endif /* defined(TARGET_PPC64) */
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#endif /* CONFIG_TCG */
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static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
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{
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@ -1293,6 +1300,7 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
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check_tlb_flush(env, false);
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}
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#ifdef CONFIG_TCG
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void helper_rfi(CPUPPCState *env)
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{
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do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
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@ -1345,8 +1353,10 @@ void helper_rfmci(CPUPPCState *env)
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/* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
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do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
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}
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#endif
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#endif /* CONFIG_TCG */
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#endif /* !defined(CONFIG_USER_ONLY) */
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#ifdef CONFIG_TCG
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void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
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uint32_t flags)
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{
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@ -1374,11 +1384,13 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
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}
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}
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#endif
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#endif
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#if !defined(CONFIG_USER_ONLY)
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/*****************************************************************************/
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/* PowerPC 601 specific instructions (POWER bridge) */
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#ifdef CONFIG_TCG
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void helper_rfsvc(CPUPPCState *env)
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{
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do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
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@ -1523,8 +1535,10 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
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book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL);
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}
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#endif
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#endif /* CONFIG_TCG */
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#endif
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#ifdef CONFIG_TCG
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void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr)
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@ -1540,3 +1554,4 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
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env->error_code = insn & 0x03FF0000;
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cpu_loop_exit(cs);
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}
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#endif
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@ -21,7 +21,6 @@
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#include "qemu/units.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "qemu/error-report.h"
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#include "qemu/qemu-print.h"
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#include "sysemu/hw_accel.h"
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@ -33,6 +32,10 @@
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#include "mmu-book3s-v3.h"
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#include "helper_regs.h"
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#ifdef CONFIG_TCG
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#include "exec/helper-proto.h"
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#endif
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/* #define DEBUG_SLB */
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#ifdef DEBUG_SLB
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@ -97,6 +100,7 @@ void dump_slb(PowerPCCPU *cpu)
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}
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}
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#ifdef CONFIG_TCG
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void helper_slbia(CPUPPCState *env, uint32_t ih)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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@ -202,6 +206,7 @@ void helper_slbieg(CPUPPCState *env, target_ulong addr)
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{
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__helper_slbie(env, addr, true);
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}
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#endif
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int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
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target_ulong esid, target_ulong vsid)
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@ -255,6 +260,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
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return 0;
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}
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#ifdef CONFIG_TCG
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static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
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target_ulong *rt)
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{
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@ -348,6 +354,7 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
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}
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return rt;
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}
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#endif
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/* Check No-Execute or Guarded Storage */
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static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
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@ -1139,12 +1146,14 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
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cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
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}
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#ifdef CONFIG_TCG
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void helper_store_lpcr(CPUPPCState *env, target_ulong val)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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ppc_store_lpcr(cpu, val);
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}
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#endif
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void ppc_hash64_init(PowerPCCPU *cpu)
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{
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@ -20,13 +20,11 @@
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "sysemu/kvm.h"
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#include "kvm_ppc.h"
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#include "mmu-hash64.h"
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#include "mmu-hash32.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "exec/log.h"
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#include "helper_regs.h"
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#include "qemu/error-report.h"
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@ -36,6 +34,10 @@
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#include "mmu-book3s-v3.h"
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#include "mmu-radix64.h"
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#ifdef CONFIG_TCG
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#endif
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/* #define DEBUG_MMU */
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/* #define DEBUG_BATS */
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/* #define DEBUG_SOFTWARE_TLB */
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@ -268,6 +270,7 @@ static inline void ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
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ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0);
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}
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#ifdef CONFIG_TCG
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static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
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int is_code, target_ulong pte0, target_ulong pte1)
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{
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@ -286,6 +289,7 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
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/* Store last way for LRU mechanism */
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env->last_way = way;
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}
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#endif
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static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, MMUAccessType access_type)
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@ -626,6 +630,7 @@ static int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
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return 0;
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}
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#ifdef CONFIG_TCG
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/* Generic TLB search function for PowerPC embedded implementations */
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static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
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uint32_t pid)
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@ -646,6 +651,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
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return ret;
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}
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#endif
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/* Helpers specific to PowerPC 40x implementations */
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static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
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@ -1420,12 +1426,14 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
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return ret;
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}
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#ifdef CONFIG_TCG
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static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, MMUAccessType access_type,
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int type)
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{
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return get_physical_address_wtlb(env, ctx, eaddr, access_type, type, 0);
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}
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#endif
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hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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@ -1752,6 +1760,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
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return ret;
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}
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#ifdef CONFIG_TCG
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/*****************************************************************************/
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/* BATs management */
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#if !defined(FLUSH_ALL_TLBS)
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@ -1941,6 +1950,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
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#endif
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}
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}
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#endif
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/*****************************************************************************/
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/* TLB management */
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@ -1986,6 +1996,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
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}
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}
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#ifdef CONFIG_TCG
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void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
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{
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#if !defined(FLUSH_ALL_TLBS)
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@ -2927,6 +2938,7 @@ void helper_check_tlb_flush_global(CPUPPCState *env)
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{
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check_tlb_flush(env, true);
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}
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#endif /* CONFIG_TCG */
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/*****************************************************************************/
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