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target/ppc: added ifdefs around TCG-only code

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excp_helper.c, mmu-hash64.c and mmu_helper.c have some function
declarations that are TCG-only, and couldn't be easily moved to a
TCG only file, so ifdefs were added around them.

We also needed ifdefs around some header files because helper-proto.h
includes trace/generated-helpers.h, which is never created when building
without TCG, and cpu_ldst.h includes tcg/tcg.h, whose containing folder
is not included as a -iquote. As future cleanup, we could change the
part of the configuration script to add those.

cpu_init.c also had a callback definition that is TCG only and could be
removed as part of a future cleanup (all the dump_statistics part is
almost never used and will become obsolete as we transition to using
decodetree).

Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Message-Id: <20210525115355.8254-3-bruno.larsen@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bruno Larsen (billionai) 2021-05-25 08:53:53 -03:00 committed by David Gibson
parent 52e9612ee9
commit 2b44e21949
4 changed files with 44 additions and 6 deletions
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2
target/ppc/cpu_init.c
View File

@ -9307,7 +9307,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = ppc_cpu_class_by_name; cc->class_by_name = ppc_cpu_class_by_name;
cc->has_work = ppc_cpu_has_work; cc->has_work = ppc_cpu_has_work;
cc->dump_state = ppc_cpu_dump_state; cc->dump_state = ppc_cpu_dump_state;
#ifdef CONFIG_TCG
cc->dump_statistics = ppc_cpu_dump_statistics; cc->dump_statistics = ppc_cpu_dump_statistics;
#endif
cc->set_pc = ppc_cpu_set_pc; cc->set_pc = ppc_cpu_set_pc;
cc->gdb_read_register = ppc_cpu_gdb_read_register; cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register; cc->gdb_write_register = ppc_cpu_gdb_write_register;

21
target/ppc/excp_helper.c
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@ -19,12 +19,15 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/main-loop.h" #include "qemu/main-loop.h"
#include "cpu.h" #include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h" #include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "internal.h" #include "internal.h"
#include "helper_regs.h" #include "helper_regs.h"
#ifdef CONFIG_TCG
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#endif
/* #define DEBUG_OP */ /* #define DEBUG_OP */
/* #define DEBUG_SOFTWARE_TLB */ /* #define DEBUG_SOFTWARE_TLB */
/* #define DEBUG_EXCEPTIONS */ /* #define DEBUG_EXCEPTIONS */
@ -1208,6 +1211,7 @@ void raise_exception_ra(CPUPPCState *env, uint32_t exception,
raise_exception_err_ra(env, exception, 0, raddr); raise_exception_err_ra(env, exception, 0, raddr);
} }
#ifdef CONFIG_TCG
void helper_raise_exception_err(CPUPPCState *env, uint32_t exception, void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
uint32_t error_code) uint32_t error_code)
{ {
@ -1218,8 +1222,10 @@ void helper_raise_exception(CPUPPCState *env, uint32_t exception)
{ {
raise_exception_err_ra(env, exception, 0, 0); raise_exception_err_ra(env, exception, 0, 0);
} }
#endif
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
#ifdef CONFIG_TCG
void helper_store_msr(CPUPPCState *env, target_ulong val) void helper_store_msr(CPUPPCState *env, target_ulong val)
{ {
uint32_t excp = hreg_store_msr(env, val, 0); uint32_t excp = hreg_store_msr(env, val, 0);
@ -1259,6 +1265,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
(env->spr[SPR_PSSCR] & PSSCR_EC); (env->spr[SPR_PSSCR] & PSSCR_EC);
} }
#endif /* defined(TARGET_PPC64) */ #endif /* defined(TARGET_PPC64) */
#endif /* CONFIG_TCG */
static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
{ {
@ -1293,6 +1300,7 @@ static inline void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr)
check_tlb_flush(env, false); check_tlb_flush(env, false);
} }
#ifdef CONFIG_TCG
void helper_rfi(CPUPPCState *env) void helper_rfi(CPUPPCState *env)
{ {
do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful); do_rfi(env, env->spr[SPR_SRR0], env->spr[SPR_SRR1] & 0xfffffffful);
@ -1345,8 +1353,10 @@ void helper_rfmci(CPUPPCState *env)
/* FIXME: choose CSRR1 or MCSRR1 based on cpu type */ /* FIXME: choose CSRR1 or MCSRR1 based on cpu type */
do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); do_rfi(env, env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
} }
#endif #endif /* CONFIG_TCG */
#endif /* !defined(CONFIG_USER_ONLY) */
#ifdef CONFIG_TCG
void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2, void helper_tw(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
uint32_t flags) uint32_t flags)
{ {
@ -1374,11 +1384,13 @@ void helper_td(CPUPPCState *env, target_ulong arg1, target_ulong arg2,
} }
} }
#endif #endif
#endif
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
/*****************************************************************************/ /*****************************************************************************/
/* PowerPC 601 specific instructions (POWER bridge) */ /* PowerPC 601 specific instructions (POWER bridge) */
#ifdef CONFIG_TCG
void helper_rfsvc(CPUPPCState *env) void helper_rfsvc(CPUPPCState *env)
{ {
do_rfi(env, env->lr, env->ctr & 0x0000FFFF); do_rfi(env, env->lr, env->ctr & 0x0000FFFF);
@ -1523,8 +1535,10 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL);
} }
#endif #endif
#endif /* CONFIG_TCG */
#endif #endif
#ifdef CONFIG_TCG
void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
MMUAccessType access_type, MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr) int mmu_idx, uintptr_t retaddr)
@ -1540,3 +1554,4 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
env->error_code = insn & 0x03FF0000; env->error_code = insn & 0x03FF0000;
cpu_loop_exit(cs); cpu_loop_exit(cs);
} }
#endif

11
target/ppc/mmu-hash64.c
View File

@ -21,7 +21,6 @@
#include "qemu/units.h" #include "qemu/units.h"
#include "cpu.h" #include "cpu.h"
#include "exec/exec-all.h" #include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
#include "qemu/qemu-print.h" #include "qemu/qemu-print.h"
#include "sysemu/hw_accel.h" #include "sysemu/hw_accel.h"
@ -33,6 +32,10 @@
#include "mmu-book3s-v3.h" #include "mmu-book3s-v3.h"
#include "helper_regs.h" #include "helper_regs.h"
#ifdef CONFIG_TCG
#include "exec/helper-proto.h"
#endif
/* #define DEBUG_SLB */ /* #define DEBUG_SLB */
#ifdef DEBUG_SLB #ifdef DEBUG_SLB
@ -97,6 +100,7 @@ void dump_slb(PowerPCCPU *cpu)
} }
} }
#ifdef CONFIG_TCG
void helper_slbia(CPUPPCState *env, uint32_t ih) void helper_slbia(CPUPPCState *env, uint32_t ih)
{ {
PowerPCCPU *cpu = env_archcpu(env); PowerPCCPU *cpu = env_archcpu(env);
@ -202,6 +206,7 @@ void helper_slbieg(CPUPPCState *env, target_ulong addr)
{ {
__helper_slbie(env, addr, true); __helper_slbie(env, addr, true);
} }
#endif
int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
target_ulong esid, target_ulong vsid) target_ulong esid, target_ulong vsid)
@ -255,6 +260,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
return 0; return 0;
} }
#ifdef CONFIG_TCG
static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb,
target_ulong *rt) target_ulong *rt)
{ {
@ -348,6 +354,7 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
} }
return rt; return rt;
} }
#endif
/* Check No-Execute or Guarded Storage */ /* Check No-Execute or Guarded Storage */
static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu,
@ -1139,12 +1146,14 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, target_ulong ptex,
cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH; cpu->env.tlb_need_flush = TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLUSH;
} }
#ifdef CONFIG_TCG
void helper_store_lpcr(CPUPPCState *env, target_ulong val) void helper_store_lpcr(CPUPPCState *env, target_ulong val)
{ {
PowerPCCPU *cpu = env_archcpu(env); PowerPCCPU *cpu = env_archcpu(env);
ppc_store_lpcr(cpu, val); ppc_store_lpcr(cpu, val);
} }
#endif
void ppc_hash64_init(PowerPCCPU *cpu) void ppc_hash64_init(PowerPCCPU *cpu)
{ {

16
target/ppc/mmu_helper.c
View File

@ -20,13 +20,11 @@
#include "qemu/osdep.h" #include "qemu/osdep.h"
#include "qemu/units.h" #include "qemu/units.h"
#include "cpu.h" #include "cpu.h"
#include "exec/helper-proto.h"
#include "sysemu/kvm.h" #include "sysemu/kvm.h"
#include "kvm_ppc.h" #include "kvm_ppc.h"
#include "mmu-hash64.h" #include "mmu-hash64.h"
#include "mmu-hash32.h" #include "mmu-hash32.h"
#include "exec/exec-all.h" #include "exec/exec-all.h"
#include "exec/cpu_ldst.h"
#include "exec/log.h" #include "exec/log.h"
#include "helper_regs.h" #include "helper_regs.h"
#include "qemu/error-report.h" #include "qemu/error-report.h"
@ -36,6 +34,10 @@
#include "mmu-book3s-v3.h" #include "mmu-book3s-v3.h"
#include "mmu-radix64.h" #include "mmu-radix64.h"
#ifdef CONFIG_TCG
#include "exec/helper-proto.h"
#include "exec/cpu_ldst.h"
#endif
/* #define DEBUG_MMU */ /* #define DEBUG_MMU */
/* #define DEBUG_BATS */ /* #define DEBUG_BATS */
/* #define DEBUG_SOFTWARE_TLB */ /* #define DEBUG_SOFTWARE_TLB */
@ -268,6 +270,7 @@ static inline void ppc6xx_tlb_invalidate_virt(CPUPPCState *env,
ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0); ppc6xx_tlb_invalidate_virt2(env, eaddr, is_code, 0);
} }
#ifdef CONFIG_TCG
static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way, static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
int is_code, target_ulong pte0, target_ulong pte1) int is_code, target_ulong pte0, target_ulong pte1)
{ {
@ -286,6 +289,7 @@ static void ppc6xx_tlb_store(CPUPPCState *env, target_ulong EPN, int way,
/* Store last way for LRU mechanism */ /* Store last way for LRU mechanism */
env->last_way = way; env->last_way = way;
} }
#endif
static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, MMUAccessType access_type) target_ulong eaddr, MMUAccessType access_type)
@ -626,6 +630,7 @@ static int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
return 0; return 0;
} }
#ifdef CONFIG_TCG
/* Generic TLB search function for PowerPC embedded implementations */ /* Generic TLB search function for PowerPC embedded implementations */
static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address, static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
uint32_t pid) uint32_t pid)
@ -646,6 +651,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
return ret; return ret;
} }
#endif
/* Helpers specific to PowerPC 40x implementations */ /* Helpers specific to PowerPC 40x implementations */
static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env) static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
@ -1420,12 +1426,14 @@ static int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
return ret; return ret;
} }
#ifdef CONFIG_TCG
static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, MMUAccessType access_type, target_ulong eaddr, MMUAccessType access_type,
int type) int type)
{ {
return get_physical_address_wtlb(env, ctx, eaddr, access_type, type, 0); return get_physical_address_wtlb(env, ctx, eaddr, access_type, type, 0);
} }
#endif
hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{ {
@ -1752,6 +1760,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
return ret; return ret;
} }
#ifdef CONFIG_TCG
/*****************************************************************************/ /*****************************************************************************/
/* BATs management */ /* BATs management */
#if !defined(FLUSH_ALL_TLBS) #if !defined(FLUSH_ALL_TLBS)
@ -1941,6 +1950,7 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
#endif #endif
} }
} }
#endif
/*****************************************************************************/ /*****************************************************************************/
/* TLB management */ /* TLB management */
@ -1986,6 +1996,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
} }
} }
#ifdef CONFIG_TCG
void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
{ {
#if !defined(FLUSH_ALL_TLBS) #if !defined(FLUSH_ALL_TLBS)
@ -2927,6 +2938,7 @@ void helper_check_tlb_flush_global(CPUPPCState *env)
{ {
check_tlb_flush(env, true); check_tlb_flush(env, true);
} }
#endif /* CONFIG_TCG */
/*****************************************************************************/ /*****************************************************************************/