target/riscv: Update VS timer whenever htimedelta changes
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a3
("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
parent
32c435a1ae
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@ -3045,6 +3045,8 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
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static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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RISCVCPU *cpu = env_archcpu(env);
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if (!env->rdtime_fn) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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@ -3054,6 +3056,12 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
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} else {
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env->htimedelta = val;
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}
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if (cpu->cfg.ext_sstc && env->rdtime_fn) {
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riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
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env->htimedelta, MIP_VSTIP);
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}
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return RISCV_EXCP_NONE;
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}
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@ -3071,11 +3079,19 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
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static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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RISCVCPU *cpu = env_archcpu(env);
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if (!env->rdtime_fn) {
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return RISCV_EXCP_ILLEGAL_INST;
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}
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env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
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if (cpu->cfg.ext_sstc && env->rdtime_fn) {
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riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
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env->htimedelta, MIP_VSTIP);
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}
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return RISCV_EXCP_NONE;
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}
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