OpenE2K/qemu-e2k
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Compile serial only once

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Push TARGET_WORDS_BIGENDIAN dependency to board level.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl 2010-03-21 19:47:11 +00:00
parent d3ffc7a6e7
commit 2d48377a85
27 changed files with 183 additions and 62 deletions
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1
Makefile.objs
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@ -138,6 +138,7 @@ hw-obj-$(CONFIG_NAND) += nand.o
hw-obj-$(CONFIG_M48T59) += m48t59.o
hw-obj-$(CONFIG_ESCC) += escc.o
hw-obj-$(CONFIG_SERIAL) += serial.o
hw-obj-$(CONFIG_PARALLEL) += parallel.o
hw-obj-$(CONFIG_I8254) += i8254.o
hw-obj-$(CONFIG_PCSPK) += pcspk.o

12
Makefile.target
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@ -197,7 +197,7 @@ obj-y += e1000.o
obj-i386-y = ide/core.o
obj-i386-y += pckbd.o $(sound-obj-y) dma.o
obj-i386-y += vga.o
obj-i386-y += mc146818rtc.o serial.o i8259.o pc.o
obj-i386-y += mc146818rtc.o i8259.o pc.o
obj-i386-y += cirrus_vga.o apic.o ioapic.o acpi.o piix_pci.o
obj-i386-y += vmmouse.o vmport.o vmware_vga.o hpet.o
obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
@ -207,7 +207,7 @@ obj-i386-y += debugcon.o multiboot.o
obj-ppc-y = ppc.o ide/core.o ide/macio.o
obj-ppc-y += vga.o $(sound-obj-y) dma.o openpic.o
# PREP target
obj-ppc-y += pckbd.o serial.o i8259.o mc146818rtc.o
obj-ppc-y += pckbd.o i8259.o mc146818rtc.o
obj-ppc-y += prep_pci.o ppc_prep.o
# Mac shared devices
obj-ppc-y += macio.o cuda.o adb.o mac_nvram.o mac_dbdma.o
@ -225,7 +225,7 @@ obj-ppc-$(CONFIG_FDT) += device_tree.o
obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o
obj-mips-y += mips_addr.o mips_timer.o mips_int.o
obj-mips-y += dma.o vga.o serial.o i8259.o rc4030.o
obj-mips-y += dma.o vga.o i8259.o rc4030.o
obj-mips-y += vga-isa-mm.o
obj-mips-y += g364fb.o jazz_led.o dp8393x.o
obj-mips-y += ide/core.o
@ -263,7 +263,7 @@ ifeq ($(TARGET_ARCH), sparc64)
obj-sparc-y = sun4u.o pckbd.o apb_pci.o
obj-sparc-y += ide/core.o
obj-sparc-y += vga.o
obj-sparc-y += mc146818rtc.o serial.o
obj-sparc-y += mc146818rtc.o
obj-sparc-y += cirrus_vga.o
else
obj-sparc-y = sun4m.o lance.o tcx.o iommu.o slavio_intctl.o
@ -281,7 +281,7 @@ obj-arm-y += arm-semi.o
obj-arm-y += pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o
obj-arm-y += pflash_cfi01.o gumstix.o
obj-arm-y += zaurus.o ide/core.o ide/microdrive.o serial.o spitz.o tosa.o tc6393xb.o
obj-arm-y += zaurus.o ide/core.o ide/microdrive.o spitz.o tosa.o tc6393xb.o
obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
obj-arm-y += omap2.o omap_dss.o soc_dma.o
obj-arm-y += omap_sx1.o palm.o tsc210x.o
@ -294,7 +294,7 @@ obj-arm-y += syborg_serial.o syborg_timer.o syborg_pointer.o syborg_rtc.o
obj-arm-y += syborg_virtio.o
obj-sh4-y = shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
obj-sh4-y += sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o
obj-sh4-y += ide/core.o ide/mmio.o
obj-m68k-y = an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o

1
default-configs/arm-softmmu.mak
View File

@ -5,6 +5,7 @@ CONFIG_USB_OHCI=y
CONFIG_ISA_MMIO=y
CONFIG_NAND=y
CONFIG_ECC=y
CONFIG_SERIAL=y
CONFIG_PTIMER=y
CONFIG_SD=y
CONFIG_MAX7310=y

1
default-configs/i386-softmmu.mak
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@ -3,6 +3,7 @@
CONFIG_USB_OHCI=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y

1
default-configs/mips-softmmu.mak
View File

@ -4,6 +4,7 @@ CONFIG_ISA_MMIO=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y

1
default-configs/mips64-softmmu.mak
View File

@ -4,6 +4,7 @@ CONFIG_ISA_MMIO=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y

1
default-configs/mips64el-softmmu.mak
View File

@ -4,6 +4,7 @@ CONFIG_ISA_MMIO=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y

1
default-configs/mipsel-softmmu.mak
View File

@ -4,6 +4,7 @@ CONFIG_ISA_MMIO=y
CONFIG_ESP=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y

1
default-configs/ppc-softmmu.mak
View File

@ -6,6 +6,7 @@ CONFIG_ISA_MMIO=y
CONFIG_ESCC=y
CONFIG_M48T59=y
CONFIG_VGA_PCI=y
CONFIG_SERIAL=y
CONFIG_I8254=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y

1
default-configs/ppc64-softmmu.mak
View File

@ -6,6 +6,7 @@ CONFIG_ISA_MMIO=y
CONFIG_ESCC=y
CONFIG_M48T59=y
CONFIG_VGA_PCI=y
CONFIG_SERIAL=y
CONFIG_I8254=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y

1
default-configs/ppcemb-softmmu.mak
View File

@ -6,6 +6,7 @@ CONFIG_ISA_MMIO=y
CONFIG_ESCC=y
CONFIG_M48T59=y
CONFIG_VGA_PCI=y
CONFIG_SERIAL=y
CONFIG_I8254=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y

1
default-configs/sh4-softmmu.mak
View File

@ -1,4 +1,5 @@
# Default configuration for sh4-softmmu
CONFIG_USB_OHCI=y
CONFIG_SERIAL=y
CONFIG_PTIMER=y

1
default-configs/sh4eb-softmmu.mak
View File

@ -1,4 +1,5 @@
# Default configuration for sh4eb-softmmu
CONFIG_USB_OHCI=y
CONFIG_SERIAL=y
CONFIG_PTIMER=y

1
default-configs/sparc64-softmmu.mak
View File

@ -4,6 +4,7 @@ CONFIG_ISA_MMIO=y
CONFIG_M48T59=y
CONFIG_PTIMER=y
CONFIG_VGA_PCI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_FDC=y
CONFIG_IDE_QDEV=y

1
default-configs/x86_64-softmmu.mak
View File

@ -3,6 +3,7 @@
CONFIG_USB_OHCI=y
CONFIG_VGA_PCI=y
CONFIG_VGA_ISA=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
CONFIG_PCSPK=y

18
hw/mips_jazz.c
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@ -254,10 +254,20 @@ void mips_jazz_init (ram_addr_t ram_size,
i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
/* Serial ports */
if (serial_hds[0])
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
if (serial_hds[1])
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
if (serial_hds[0]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 1);
#else
serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1, 0);
#endif
}
if (serial_hds[1]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 1);
#else
serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1, 0);
#endif
}
/* Parallel port */
if (parallel_hds[0])

6
hw/mips_malta.c
View File

@ -441,7 +441,11 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir
s->display = qemu_chr_open("fpga", "vc:320x200", malta_fpga_led_init);
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1);
#ifdef TARGET_WORDS_BIGENDIAN
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 1);
#else
s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1, 0);
#endif
malta_fpga_reset(s);
qemu_register_reset(malta_fpga_reset, s);

14
hw/musicpal.c
View File

@ -1525,12 +1525,22 @@ static void musicpal_init(ram_addr_t ram_size,
pic[MP_TIMER4_IRQ], NULL);
if (serial_hds[0]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
serial_hds[0], 1);
serial_hds[0], 1, 1);
#else
serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
serial_hds[0], 1, 0);
#endif
}
if (serial_hds[1]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
serial_hds[1], 1);
serial_hds[1], 1, 1);
#else
serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
serial_hds[1], 1, 0);
#endif
}
/* Register flash */

22
hw/omap1.c
View File

@ -1986,9 +1986,15 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
s->base = base;
s->fclk = fclk;
s->irq = irq;
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_open("null", "null", NULL), 1);
chr ?: qemu_chr_open("null", "null", NULL), 1,
1);
#else
s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
chr ?: qemu_chr_open("null", "null", NULL), 1,
0);
#endif
return s;
}
@ -2101,9 +2107,17 @@ struct omap_uart_s *omap2_uart_init(struct omap_target_agent_s *ta,
void omap_uart_attach(struct omap_uart_s *s, CharDriverState *chr)
{
/* TODO: Should reuse or destroy current s->serial */
#ifdef TARGET_WORDS_BIGENDIAN
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_open("null", "null", NULL), 1);
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_open("null", "null", NULL), 1,
1);
#else
s->serial = serial_mm_init(s->base, 2, s->irq,
omap_clk_getrate(s->fclk) / 16,
chr ?: qemu_chr_open("null", "null", NULL), 1,
0);
#endif
}
/* MPU Clock/Reset/Power Mode Control */

3
hw/pc.h
View File

@ -12,7 +12,8 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr);
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, int ioregister);
CharDriverState *chr, int ioregister,
int be);
SerialState *serial_isa_init(int index, CharDriverState *chr);
void serial_set_frequency(SerialState *s, uint32_t frequency);

8
hw/ppc405_uc.c
View File

@ -2182,11 +2182,11 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
/* Serial ports */
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1);
serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1);
serial_hds[1], 1, 1);
}
/* IIC controller */
ppc405_i2c_init(0xef600500, pic[2]);
@ -2535,11 +2535,11 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
/* Serial ports */
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1);
serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1);
serial_hds[1], 1, 1);
}
/* OCM */
ppc405_ocm_init(env);

4
hw/ppc440.c
View File

@ -89,11 +89,11 @@ CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
serial_hds[0], 1);
serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
serial_hds[1], 1);
serial_hds[1], 1, 1);
}
return env;

14
hw/ppce500_mpc8544ds.c
View File

@ -198,15 +198,17 @@ static void mpc8544ds_init(ram_addr_t ram_size,
mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
/* Serial */
if (serial_hds[0])
if (serial_hds[0]) {
serial[0] = serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], 1);
0, mpic[12+26], 399193,
serial_hds[0], 1, 1);
}
if (serial_hds[1])
if (serial_hds[1]) {
serial[0] = serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
0, mpic[12+26], 399193,
serial_hds[0], 1);
0, mpic[12+26], 399193,
serial_hds[0], 1, 1);
}
/* PCI */
pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);

21
hw/pxa2xx.c
View File

@ -2076,9 +2076,15 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
for (i = 0; pxa270_serial[i].io_base; i ++)
if (serial_hds[i])
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa270_serial[i].io_base, 2,
s->pic[pxa270_serial[i].irqn], 14857000/16,
serial_hds[i], 1);
serial_hds[i], 1, 1);
#else
serial_mm_init(pxa270_serial[i].io_base, 2,
s->pic[pxa270_serial[i].irqn], 14857000/16,
serial_hds[i], 1, 1);
#endif
else
break;
if (serial_hds[i])
@ -2187,12 +2193,19 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
s->pic[PXA2XX_PIC_MMC], s->dma);
for (i = 0; pxa255_serial[i].io_base; i ++)
if (serial_hds[i])
if (serial_hds[i]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa255_serial[i].io_base, 2,
s->pic[pxa255_serial[i].irqn], 14745600/16,
serial_hds[i], 1);
else
serial_hds[i], 1, 1);
#else
serial_mm_init(pxa255_serial[i].io_base, 2,
s->pic[pxa255_serial[i].irqn], 14745600/16,
serial_hds[i], 1, 0);
#endif
} else {
break;
}
if (serial_hds[i])
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);

92
hw/serial.c
View File

@ -825,65 +825,106 @@ static void serial_mm_writeb(void *opaque, target_phys_addr_t addr,
serial_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
static uint32_t serial_mm_readw(void *opaque, target_phys_addr_t addr)
static uint32_t serial_mm_readw_be(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
return val;
}
static void serial_mm_writew(void *opaque, target_phys_addr_t addr,
uint32_t value)
static uint32_t serial_mm_readw_le(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
uint32_t val;
val = serial_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
return val;
}
static void serial_mm_writew_be(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
SerialState *s = opaque;
value = bswap16(value);
#endif
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
static uint32_t serial_mm_readl(void *opaque, target_phys_addr_t addr)
static void serial_mm_writew_le(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
SerialState *s = opaque;
serial_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
static uint32_t serial_mm_readl_be(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
uint32_t val;
val = serial_ioport_read(s, addr >> s->it_shift);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
return val;
}
static void serial_mm_writel(void *opaque, target_phys_addr_t addr,
uint32_t value)
static uint32_t serial_mm_readl_le(void *opaque, target_phys_addr_t addr)
{
SerialState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
uint32_t val;
val = serial_ioport_read(s, addr >> s->it_shift);
return val;
}
static void serial_mm_writel_be(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
SerialState *s = opaque;
value = bswap32(value);
#endif
serial_ioport_write(s, addr >> s->it_shift, value);
}
static CPUReadMemoryFunc * const serial_mm_read[] = {
static void serial_mm_writel_le(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
SerialState *s = opaque;
serial_ioport_write(s, addr >> s->it_shift, value);
}
static CPUReadMemoryFunc * const serial_mm_read_be[] = {
&serial_mm_readb,
&serial_mm_readw,
&serial_mm_readl,
&serial_mm_readw_be,
&serial_mm_readl_be,
};
static CPUWriteMemoryFunc * const serial_mm_write[] = {
static CPUWriteMemoryFunc * const serial_mm_write_be[] = {
&serial_mm_writeb,
&serial_mm_writew,
&serial_mm_writel,
&serial_mm_writew_be,
&serial_mm_writel_be,
};
static CPUReadMemoryFunc * const serial_mm_read_le[] = {
&serial_mm_readb,
&serial_mm_readw_le,
&serial_mm_readl_le,
};
static CPUWriteMemoryFunc * const serial_mm_write_le[] = {
&serial_mm_writeb,
&serial_mm_writew_le,
&serial_mm_writel_le,
};
SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, int ioregister)
CharDriverState *chr, int ioregister,
int be)
{
SerialState *s;
int s_io_memory;
@ -899,8 +940,13 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
vmstate_register(base, &vmstate_serial, s);
if (ioregister) {
s_io_memory = cpu_register_io_memory(serial_mm_read,
serial_mm_write, s);
if (be) {
s_io_memory = cpu_register_io_memory(serial_mm_read_be,
serial_mm_write_be, s);
} else {
s_io_memory = cpu_register_io_memory(serial_mm_read_le,
serial_mm_write_le, s);
}
cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
}
serial_update_msl(s);

15
hw/sm501.c
View File

@ -1226,10 +1226,17 @@ void sm501_init(uint32_t base, uint32_t local_mem_bytes, qemu_irq irq,
2, -1, irq);
/* bridge to serial emulation module */
if (chr)
serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
115200, chr, 1);
if (chr) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
115200, chr, 1, 1);
#else
serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
NULL, /* TODO : chain irq to IRL */
115200, chr, 1, 0);
#endif
}
/* create qemu graphic console */
s->ds = graphic_console_init(sm501_update_display, NULL,

2
hw/sun4u.c
View File

@ -771,7 +771,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
i = 0;
if (hwdef->console_serial_base) {
serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
serial_hds[i], 1);
serial_hds[i], 1, 1);
i++;
}
for(; i < MAX_SERIAL_PORTS; i++) {