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target/nios2: Implement CR_STATUS.RSIE 

Without EIC, this bit is RES1.  So set the bit at reset,
and add it to the readonly fields of CR_STATUS.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220421151735.31996-40-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-21 08:17:10 -07:00
parent b05550af11
commit 2de70d2d96
1 changed files with 3 additions and 2 deletions
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5
target/nios2/cpu.c
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@ -54,9 +54,9 @@ static void nios2_cpu_reset(DeviceState *dev)
#if defined(CONFIG_USER_ONLY)
/* Start in user mode with interrupts enabled. */
env->ctrl[CR_STATUS] = CR_STATUS_U | CR_STATUS_PIE;
env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE;
#else
env->ctrl[CR_STATUS] = 0;
env->ctrl[CR_STATUS] = CR_STATUS_RSIE;
#endif
}
@ -127,6 +127,7 @@ static void realize_cr_status(CPUState *cs)
WR_REG(CR_BADADDR);
/* TODO: These control registers are not present with the EIC. */
RO_FIELD(CR_STATUS, RSIE);
WR_REG(CR_IENABLE);
RO_REG(CR_IPENDING);