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target/loongarch: Implement vclo vclz 

This patch includes:
- VCLO.{B/H/W/D};
- VCLZ.{B/H/W/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-30-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:55 +08:00
parent 162cd32cfe
commit 2e105e12a5
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
5 changed files with 67 additions and 0 deletions
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9
target/loongarch/disas.c
View File

@ -1258,3 +1258,12 @@ INSN_LSX(vssrarni_bu_h, vv_i)
INSN_LSX(vssrarni_hu_w, vv_i)
INSN_LSX(vssrarni_wu_d, vv_i)
INSN_LSX(vssrarni_du_q, vv_i)
INSN_LSX(vclo_b, vv)
INSN_LSX(vclo_h, vv)
INSN_LSX(vclo_w, vv)
INSN_LSX(vclo_d, vv)
INSN_LSX(vclz_b, vv)
INSN_LSX(vclz_h, vv)
INSN_LSX(vclz_w, vv)
INSN_LSX(vclz_d, vv)

9
target/loongarch/helper.h
View File

@ -471,3 +471,12 @@ DEF_HELPER_4(vssrarni_bu_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_hu_w, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_wu_d, void, env, i32, i32, i32)
DEF_HELPER_4(vssrarni_du_q, void, env, i32, i32, i32)
DEF_HELPER_3(vclo_b, void, env, i32, i32)
DEF_HELPER_3(vclo_h, void, env, i32, i32)
DEF_HELPER_3(vclo_w, void, env, i32, i32)
DEF_HELPER_3(vclo_d, void, env, i32, i32)
DEF_HELPER_3(vclz_b, void, env, i32, i32)
DEF_HELPER_3(vclz_h, void, env, i32, i32)
DEF_HELPER_3(vclz_w, void, env, i32, i32)
DEF_HELPER_3(vclz_d, void, env, i32, i32)

9
target/loongarch/insn_trans/trans_lsx.c.inc
View File

@ -3097,3 +3097,12 @@ TRANS(vssrarni_bu_h, gen_vv_i, gen_helper_vssrarni_bu_h)
TRANS(vssrarni_hu_w, gen_vv_i, gen_helper_vssrarni_hu_w)
TRANS(vssrarni_wu_d, gen_vv_i, gen_helper_vssrarni_wu_d)
TRANS(vssrarni_du_q, gen_vv_i, gen_helper_vssrarni_du_q)
TRANS(vclo_b, gen_vv, gen_helper_vclo_b)
TRANS(vclo_h, gen_vv, gen_helper_vclo_h)
TRANS(vclo_w, gen_vv, gen_helper_vclo_w)
TRANS(vclo_d, gen_vv, gen_helper_vclo_d)
TRANS(vclz_b, gen_vv, gen_helper_vclz_b)
TRANS(vclz_h, gen_vv, gen_helper_vclz_h)
TRANS(vclz_w, gen_vv, gen_helper_vclz_w)
TRANS(vclz_d, gen_vv, gen_helper_vclz_d)

9
target/loongarch/insns.decode
View File

@ -959,3 +959,12 @@ vssrarni_bu_h 0111 00110110 11000 1 .... ..... ..... @vv_ui4
vssrarni_hu_w 0111 00110110 11001 ..... ..... ..... @vv_ui5
vssrarni_wu_d 0111 00110110 1101 ...... ..... ..... @vv_ui6
vssrarni_du_q 0111 00110110 111 ....... ..... ..... @vv_ui7
vclo_b 0111 00101001 11000 00000 ..... ..... @vv
vclo_h 0111 00101001 11000 00001 ..... ..... @vv
vclo_w 0111 00101001 11000 00010 ..... ..... @vv
vclo_d 0111 00101001 11000 00011 ..... ..... @vv
vclz_b 0111 00101001 11000 00100 ..... ..... @vv
vclz_h 0111 00101001 11000 00101 ..... ..... @vv
vclz_w 0111 00101001 11000 00110 ..... ..... @vv
vclz_d 0111 00101001 11000 00111 ..... ..... @vv

31
target/loongarch/lsx_helper.c
View File

@ -1915,3 +1915,34 @@ void HELPER(vssrarni_du_q)(CPULoongArchState *env,
VSSRARNUI(vssrarni_bu_h, 16, B, H)
VSSRARNUI(vssrarni_hu_w, 32, H, W)
VSSRARNUI(vssrarni_wu_d, 64, W, D)
#define DO_2OP(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(CPULoongArchState *env, uint32_t vd, uint32_t vj) \
{ \
int i; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
\
for (i = 0; i < LSX_LEN/BIT; i++) \
{ \
Vd->E(i) = DO_OP(Vj->E(i)); \
} \
}
#define DO_CLO_B(N) (clz32(~N & 0xff) - 24)
#define DO_CLO_H(N) (clz32(~N & 0xffff) - 16)
#define DO_CLO_W(N) (clz32(~N))
#define DO_CLO_D(N) (clz64(~N))
#define DO_CLZ_B(N) (clz32(N) - 24)
#define DO_CLZ_H(N) (clz32(N) - 16)
#define DO_CLZ_W(N) (clz32(N))
#define DO_CLZ_D(N) (clz64(N))
DO_2OP(vclo_b, 8, UB, DO_CLO_B)
DO_2OP(vclo_h, 16, UH, DO_CLO_H)
DO_2OP(vclo_w, 32, UW, DO_CLO_W)
DO_2OP(vclo_d, 64, UD, DO_CLO_D)
DO_2OP(vclz_b, 8, UB, DO_CLZ_B)
DO_2OP(vclz_h, 16, UH, DO_CLZ_H)
DO_2OP(vclz_w, 32, UW, DO_CLZ_W)
DO_2OP(vclz_d, 64, UD, DO_CLZ_D)