diff --git a/target-arm/op.c b/target-arm/op.c
index 5879eba9fd..73f95b7774 100644
--- a/target-arm/op.c
+++ b/target-arm/op.c
@@ -368,7 +368,7 @@ void OPPROTO op_mul_T0_T1(void)
 void OPPROTO op_mull_T0_T1(void)
 {
     uint64_t res;
-    res = T0 * T1;
+    res = (uint64_t)T0 * (uint64_t)T1;
     T1 = res >> 32;
     T0 = res;
 }
@@ -377,7 +377,7 @@ void OPPROTO op_mull_T0_T1(void)
 void OPPROTO op_imull_T0_T1(void)
 {
     uint64_t res;
-    res = (int32_t)T0 * (int32_t)T1;
+    res = (int64_t)T0 * (int64_t)T1;
     T1 = res >> 32;
     T0 = res;
 }
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 808fa2b34f..9447946293 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -516,9 +516,9 @@ static void disas_arm_insn(DisasContext *s)
                         gen_movl_T0_reg(s, rs);
                         gen_movl_T1_reg(s, rm);
                         if (insn & (1 << 22)) 
-                            gen_op_mull_T0_T1();
-                        else
                             gen_op_imull_T0_T1();
+                        else
+                            gen_op_mull_T0_T1();
                         if (insn & (1 << 21)) 
                             gen_op_addq_T0_T1(rn, rd);
                         if (insn & (1 << 20))