PPC: e500: Move CCSR definition to params
We want to have different MMIO region offsets for the mpc8544ds machine and our e500 PV machine, so move the definitions of those into the machine specific params struct. Signed-off-by: Alexander Graf <agraf@suse.de>
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Alexander Graf
parent
ab0302ee76
commit
2eaaac1f01
@ -51,19 +51,14 @@
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#define RAM_SIZES_ALIGN (64UL << 20)
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/* TODO: parameterize */
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#define MPC8544_CCSRBAR_BASE 0xE0000000ULL
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#define MPC8544_CCSRBAR_SIZE 0x00100000ULL
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#define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
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#define MPC8544_MSI_REGS_OFFSET 0x41600ULL
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#define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
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#define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
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#define MPC8544_PCI_REGS_OFFSET 0x8000ULL
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#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
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MPC8544_PCI_REGS_OFFSET)
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#define MPC8544_PCI_REGS_SIZE 0x1000ULL
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#define MPC8544_PCI_IO 0xE1000000ULL
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#define MPC8544_UTIL_OFFSET 0xe0000ULL
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#define MPC8544_SPIN_BASE 0xEF000000ULL
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#define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
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#define MPC8XXX_GPIO_IRQ 43
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@ -298,7 +293,7 @@ static int ppce500_load_device_tree(MachineState *machine,
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0x0, 0x20000000,
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0x1000000, 0x0, 0x0,
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0x0, 0xe1000000,
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params->pci_pio_base >> 32, params->pci_pio_base,
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0x0, 0x10000,
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};
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QemuOpts *machine_opts = qemu_get_machine_opts();
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@ -389,7 +384,7 @@ static int ppce500_load_device_tree(MachineState *machine,
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CPUState *cpu;
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PowerPCCPU *pcpu;
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char cpu_name[128];
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uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
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uint64_t cpu_release_addr = params->spin_base + (i * 0x20);
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cpu = qemu_get_cpu(i);
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if (cpu == NULL) {
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@ -426,7 +421,7 @@ static int ppce500_load_device_tree(MachineState *machine,
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qemu_fdt_add_subnode(fdt, "/aliases");
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/* XXX These should go into their respective devices' code */
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snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
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snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base);
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qemu_fdt_add_subnode(fdt, soc);
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qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
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qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
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@ -434,7 +429,7 @@ static int ppce500_load_device_tree(MachineState *machine,
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qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
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qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
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qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
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MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
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params->ccsrbar_base >> 32, params->ccsrbar_base,
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MPC8544_CCSRBAR_SIZE);
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/* XXX should contain a reasonable value */
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qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
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@ -493,7 +488,8 @@ static int ppce500_load_device_tree(MachineState *machine,
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qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
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qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
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snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
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snprintf(pci, sizeof(pci), "/pci@%llx",
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params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
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qemu_fdt_add_subnode(fdt, pci);
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qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
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qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
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@ -512,8 +508,10 @@ static int ppce500_load_device_tree(MachineState *machine,
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}
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qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
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qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
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qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
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MPC8544_PCI_REGS_BASE, 0, 0x1000);
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qemu_fdt_setprop_cells(fdt, pci, "reg",
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(params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
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(params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
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0, 0x1000);
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qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
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qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
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qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
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@ -841,7 +839,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
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irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
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irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
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env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
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env->mpic_iack = MPC8544_CCSRBAR_BASE +
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env->mpic_iack = params->ccsrbar_base +
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MPC8544_MPIC_REGS_OFFSET + 0xa0;
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ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
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@ -875,7 +873,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
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qdev_init_nofail(dev);
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ccsr = CCSR(dev);
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ccsr_addr_space = &ccsr->ccsr_space;
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memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
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memory_region_add_subregion(address_space_mem, params->ccsrbar_base,
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ccsr_addr_space);
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mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
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@ -917,7 +915,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
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if (!pci_bus)
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printf("couldn't create PCI controller!\n");
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, params->pci_pio_base);
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if (pci_bus) {
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/* Register network interfaces. */
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@ -927,7 +925,7 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
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}
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/* Register spinning region */
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sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
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sysbus_create_simple("e500-spin", params->spin_base, NULL);
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if (cur_base < (32 * 1024 * 1024)) {
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/* u-boot occupies memory up to 32MB, so load blobs above */
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@ -17,6 +17,9 @@ typedef struct PPCE500Params {
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hwaddr platform_bus_size;
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int platform_bus_first_irq;
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int platform_bus_num_irqs;
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hwaddr ccsrbar_base;
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hwaddr pci_pio_base;
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hwaddr spin_base;
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} PPCE500Params;
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void ppce500_init(MachineState *machine, PPCE500Params *params);
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@ -41,6 +41,9 @@ static void e500plat_init(MachineState *machine)
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.platform_bus_size = (128ULL * 1024 * 1024),
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.platform_bus_first_irq = 5,
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.platform_bus_num_irqs = 10,
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.ccsrbar_base = 0xE0000000ULL,
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.pci_pio_base = 0xE1000000ULL,
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.spin_base = 0xEF000000ULL,
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};
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/* Older KVM versions don't support EPR which breaks guests when we announce
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@ -33,6 +33,9 @@ static void mpc8544ds_init(MachineState *machine)
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.pci_nr_slots = 2,
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.fixup_devtree = mpc8544ds_fixup_devtree,
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.mpic_version = OPENPIC_MODEL_FSL_MPIC_20,
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.ccsrbar_base = 0xE0000000ULL,
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.pci_pio_base = 0xE1000000ULL,
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.spin_base = 0xEF000000ULL,
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};
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ppce500_init(machine, ¶ms);
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