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graphical_console_init change (Stefano Stabellini) 

Patch 5/7

This patch changes the graphical_console_init function to return an
allocated DisplayState instead of a QEMUConsole.

This patch contains just the graphical_console_init change and few other
modifications mainly in console.c and vl.c.
It was necessary to move the display frontends (e.g. sdl and vnc)
initialization after machine->init in vl.c.

This patch does *not* include any required changes to any device, these
changes come with the following patches.

Patch 6/7

This patch changes the QEMUMachine init functions not to take a
DisplayState as an argument because is not needed any more;

In few places the graphic hardware initialization function was called
only if DisplayState was not NULL, now they are always called.
Apart from these cases, the rest are all mechanical substitutions.

Patch 7/7

This patch updates the graphic device code to use the new
graphical_console_init function.

As for the previous patch, in few places graphical_console_init was called
only if DisplayState was not NULL, now it is always called.
Apart from these cases, the rest are all mechanical substitutions.

Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6344 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori 2009-01-16 19:04:14 +00:00
parent 9f8df9c10f
commit 3023f3329d
63 changed files with 412 additions and 407 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

60
console.c
View File

@ -1190,6 +1190,17 @@ static void text_console_update(void *opaque, console_ch_t *chardata)
}
}
static TextConsole *get_graphic_console() {
int i;
TextConsole *s;
for (i = 0; i < nb_consoles; i++) {
s = consoles[i];
if (s->console_type == GRAPHIC_CONSOLE)
return s;
}
return NULL;
}
static TextConsole *new_console(DisplayState *ds, console_type_t console_type)
{
TextConsole *s;
@ -1217,27 +1228,39 @@ static TextConsole *new_console(DisplayState *ds, console_type_t console_type)
consoles[i] = consoles[i - 1];
}
consoles[i] = s;
nb_consoles++;
}
return s;
}
TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
vga_hw_screen_dump_ptr screen_dump,
vga_hw_text_update_ptr text_update,
void *opaque)
DisplayState *graphic_console_init(vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
vga_hw_screen_dump_ptr screen_dump,
vga_hw_text_update_ptr text_update,
void *opaque)
{
TextConsole *s;
DisplayState *ds;
ds = (DisplayState *) qemu_mallocz(sizeof(DisplayState));
if (ds == NULL)
return NULL;
ds->surface = qemu_create_displaysurface(640, 480, 32, 640 * 4);
s = new_console(ds, GRAPHIC_CONSOLE);
if (!s)
return NULL;
if (s == NULL) {
qemu_free_displaysurface(ds->surface);
qemu_free(ds);
return NULL;
}
s->hw_update = update;
s->hw_invalidate = invalidate;
s->hw_screen_dump = screen_dump;
s->hw_text_update = text_update;
s->hw = opaque;
return s;
register_displaystate(ds);
return ds;
}
int is_graphic_console(void)
@ -1285,6 +1308,7 @@ CharDriverState *text_console_init(DisplayState *ds, const char *p)
s->out_fifo.buf = s->out_fifo_buf;
s->out_fifo.buf_size = sizeof(s->out_fifo_buf);
s->kbd_timer = qemu_new_timer(rt_clock, kbd_send_chars, s);
s->ds = ds;
if (!color_inited) {
color_inited = 1;
@ -1337,22 +1361,22 @@ CharDriverState *text_console_init(DisplayState *ds, const char *p)
return chr;
}
void qemu_console_resize(QEMUConsole *console, int width, int height)
void qemu_console_resize(DisplayState *ds, int width, int height)
{
console->g_width = width;
console->g_height = height;
if (active_console == console) {
DisplayState *ds = console->ds;
TextConsole *s = get_graphic_console();
s->g_width = width;
s->g_height = height;
if (is_graphic_console()) {
ds->surface = qemu_resize_displaysurface(ds->surface, width, height, 32, 4 * width);
dpy_resize(console->ds);
dpy_resize(ds);
}
}
void qemu_console_copy(QEMUConsole *console, int src_x, int src_y,
int dst_x, int dst_y, int w, int h)
void qemu_console_copy(DisplayState *ds, int src_x, int src_y,
int dst_x, int dst_y, int w, int h)
{
if (active_console == console) {
dpy_copy(console->ds, src_x, src_y, dst_x, dst_y, w, h);
if (is_graphic_console()) {
dpy_copy(ds, src_x, src_y, dst_x, dst_y, w, h);
}
}

21
console.h
View File

@ -122,8 +122,12 @@ struct DisplayState {
void (*mouse_set)(int x, int y, int on);
void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
uint8_t *image, uint8_t *mask);
struct DisplayState *next;
};
void register_displaystate(DisplayState *ds);
DisplayState *get_displaystate(void);
DisplaySurface* qemu_create_displaysurface(int width, int height, int bpp, int linesize);
DisplaySurface* qemu_resize_displaysurface(DisplaySurface *surface,
int width, int height, int bpp, int linesize);
@ -248,11 +252,12 @@ typedef void (*vga_hw_invalidate_ptr)(void *);
typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
typedef void (*vga_hw_text_update_ptr)(void *, console_ch_t *);
TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
vga_hw_screen_dump_ptr screen_dump,
vga_hw_text_update_ptr text_update,
void *opaque);
DisplayState *graphic_console_init(vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
vga_hw_screen_dump_ptr screen_dump,
vga_hw_text_update_ptr text_update,
void *opaque);
void vga_hw_update(void);
void vga_hw_invalidate(void);
void vga_hw_screen_dump(const char *filename);
@ -263,9 +268,9 @@ int is_fixedsize_console(void);
CharDriverState *text_console_init(DisplayState *ds, const char *p);
void console_select(unsigned int index);
void console_color_init(DisplayState *ds);
void qemu_console_resize(QEMUConsole *console, int width, int height);
void qemu_console_copy(QEMUConsole *console, int src_x, int src_y,
int dst_x, int dst_y, int w, int h);
void qemu_console_resize(DisplayState *ds, int width, int height);
void qemu_console_copy(DisplayState *ds, int src_x, int src_y,
int dst_x, int dst_y, int w, int h);
/* sdl.c */
void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);

2
hw/an5206.c
View File

@ -27,7 +27,7 @@ void irq_info(void)
/* Board init. */
static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{

12
hw/blizzard.c
View File

@ -72,7 +72,6 @@ struct blizzard_s {
uint8_t iformat;
uint8_t source;
DisplayState *state;
QEMUConsole *console;
blizzard_fn_t *line_fn_tab[2];
void *fb;
@ -896,7 +895,7 @@ static void blizzard_update_display(void *opaque)
if (s->x != ds_get_width(s->state) || s->y != ds_get_height(s->state)) {
s->invalidate = 1;
qemu_console_resize(s->console, s->x, s->y);
qemu_console_resize(s->state, s->x, s->y);
}
if (s->invalidate) {
@ -954,11 +953,10 @@ static void blizzard_screen_dump(void *opaque, const char *filename) {
#define DEPTH 32
#include "blizzard_template.h"
void *s1d13745_init(qemu_irq gpio_int, DisplayState *ds)
void *s1d13745_init(qemu_irq gpio_int)
{
struct blizzard_s *s = (struct blizzard_s *) qemu_mallocz(sizeof(*s));
s->state = ds;
s->fb = qemu_malloc(0x180000);
switch (ds_get_bits_per_pixel(s->state)) {
@ -993,9 +991,9 @@ void *s1d13745_init(qemu_irq gpio_int, DisplayState *ds)
blizzard_reset(s);
s->console = graphic_console_init(s->state, blizzard_update_display,
blizzard_invalidate_display,
blizzard_screen_dump, NULL, s);
s->state = graphic_console_init(blizzard_update_display,
blizzard_invalidate_display,
blizzard_screen_dump, NULL, s);
return s;
}

2
hw/boards.h
View File

@ -4,7 +4,7 @@
#define HW_BOARDS_H
typedef void QEMUMachineInitFunc(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,

18
hw/cirrus_vga.c
View File

@ -774,7 +774,7 @@ static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
s->cirrus_blt_width, s->cirrus_blt_height);
if (notify)
qemu_console_copy(s->console,
qemu_console_copy(s->ds,
sx, sy, dx, dy,
s->cirrus_blt_width / depth,
s->cirrus_blt_height);
@ -3290,7 +3290,7 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
*
***************************************/
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
void isa_cirrus_vga_init(uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size)
{
CirrusVGAState *s;
@ -3298,10 +3298,10 @@ void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
s = qemu_mallocz(sizeof(CirrusVGAState));
vga_common_init((VGAState *)s,
ds, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_ram_base, vga_ram_offset, vga_ram_size);
cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
s->console = graphic_console_init(s->ds, s->update, s->invalidate,
s->screen_dump, s->text_update, s);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
/* XXX ISA-LFB support */
}
@ -3339,7 +3339,7 @@ static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
s->cirrus_mmio_io_addr);
}
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size)
{
PCICirrusVGAState *d;
@ -3366,11 +3366,11 @@ void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
/* setup VGA */
s = &d->cirrus_vga;
vga_common_init((VGAState *)s,
ds, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_ram_base, vga_ram_offset, vga_ram_size);
cirrus_init_common(s, device_id, 1);
s->console = graphic_console_init(s->ds, s->update, s->invalidate,
s->screen_dump, s->text_update, s);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
s->pci_dev = (PCIDevice *)d;

8
hw/devices.h
View File

@ -8,7 +8,7 @@ void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
/* ssd0323.c */
int ssd0323_xfer_ssi(void *opaque, int data);
void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p);
void *ssd0323_init(qemu_irq *cmd_p);
/* ads7846.c */
struct ads7846_state_s;
@ -37,7 +37,7 @@ void tsc2005_set_transform(void *opaque, struct mouse_transform_info_s *info);
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
/* blizzard.c */
void *s1d13745_init(qemu_irq gpio_int, DisplayState *ds);
void *s1d13745_init(qemu_irq gpio_int);
void s1d13745_write(void *opaque, int dc, uint16_t value);
void s1d13745_write_block(void *opaque, int dc,
void *buf, size_t len, int pitch);
@ -67,13 +67,13 @@ void tusb6010_power(struct tusb_s *s, int on);
/* tc6393xb.c */
struct tc6393xb_s;
#define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */
struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq, DisplayState *ds);
struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq);
void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
qemu_irq handler);
qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s);
qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s);
/* sm501.c */
void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
void sm501_init(uint32_t base, unsigned long local_mem_base,
uint32_t local_mem_bytes, CharDriverState *chr);
#endif

2
hw/dummy_m68k.c
View File

@ -15,7 +15,7 @@
/* Board init. */
static void dummy_m68k_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{

2
hw/etraxfs.c
View File

@ -47,7 +47,7 @@ static void main_cpu_reset(void *opaque)
static
void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{

14
hw/g364fb.c
View File

@ -32,7 +32,6 @@ typedef struct G364State {
uint8_t palette[256][3];
/* display refresh support */
DisplayState *ds;
QEMUConsole *console;
int graphic_mode;
uint32_t scr_width, scr_height; /* in pixels */
} G364State;
@ -131,7 +130,7 @@ static void g364fb_update_display(void *opaque)
full_update = 1;
}
if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
qemu_console_resize(s->console, s->scr_width, s->scr_height);
qemu_console_resize(s->ds, s->scr_width, s->scr_height);
full_update = 1;
}
switch(graphic_mode) {
@ -354,8 +353,7 @@ static CPUWriteMemoryFunc *g364fb_mem_write[3] = {
g364fb_mem_writel,
};
int g364fb_mm_init(DisplayState *ds,
int vram_size, int it_shift,
int g364fb_mm_init(int vram_size, int it_shift,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
{
G364State *s;
@ -371,11 +369,9 @@ int g364fb_mm_init(DisplayState *ds,
qemu_register_reset(g364fb_reset, s);
g364fb_reset(s);
s->ds = ds;
s->console = graphic_console_init(ds, g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
s->ds = graphic_console_init(g364fb_update_display,
g364fb_invalidate_display,
g364fb_screen_dump, NULL, s);
io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
cpu_register_physical_memory(vram_base, vram_size, io_vram);

8
hw/gumstix.c
View File

@ -42,7 +42,7 @@
static const int sector_len = 128 * 1024;
static void connex_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -58,7 +58,7 @@ static void connex_init(ram_addr_t ram_size, int vga_ram_size,
exit(1);
}
cpu = pxa255_init(connex_ram, ds);
cpu = pxa255_init(connex_ram);
index = drive_get_index(IF_PFLASH, 0, 0);
if (index == -1) {
@ -82,7 +82,7 @@ static void connex_init(ram_addr_t ram_size, int vga_ram_size,
}
static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -98,7 +98,7 @@ static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
exit(1);
}
cpu = pxa270_init(verdex_ram, ds, cpu_model ?: "pxa270-c0");
cpu = pxa270_init(verdex_ram, cpu_model ?: "pxa270-c0");
index = drive_get_index(IF_PFLASH, 0, 0);
if (index == -1) {

2
hw/i2c.h
View File

@ -71,7 +71,7 @@ void wm8750_dac_commit(void *opaque);
void wm8750_set_bclk_in(void *opaque, int new_hz);
/* ssd0303.c */
void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address);
void ssd0303_init(i2c_bus *bus, int address);
/* twl92230.c */
i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq);

4
hw/integratorcp.c
View File

@ -454,7 +454,7 @@ static struct arm_boot_info integrator_binfo = {
};
static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -499,7 +499,7 @@ static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
pl181_init(0x1c000000, drives_table[sd].bdrv, pic[23], pic[24]);
if (nd_table[0].vlan)
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
pl110_init(ds, 0xc0000000, pic[22], 0);
pl110_init(0xc0000000, pic[22], 0);
integrator_binfo.ram_size = ram_size;
integrator_binfo.kernel_filename = kernel_filename;

16
hw/jazz_led.c
View File

@ -36,7 +36,6 @@ typedef enum {
typedef struct LedState {
uint8_t segments;
DisplayState *ds;
QEMUConsole *console;
screen_state_t state;
} LedState;
@ -289,7 +288,7 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
char buf[2];
dpy_cursor(s->ds, -1, -1);
qemu_console_resize(s->console, 2, 1);
qemu_console_resize(s->ds, 2, 1);
/* TODO: draw the segments */
snprintf(buf, 2, "%02hhx\n", s->segments);
@ -299,7 +298,7 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata)
dpy_update(s->ds, 0, 0, 2, 1);
}
void jazz_led_init(DisplayState *ds, target_phys_addr_t base)
void jazz_led_init(target_phys_addr_t base)
{
LedState *s;
int io;
@ -308,15 +307,14 @@ void jazz_led_init(DisplayState *ds, target_phys_addr_t base)
if (!s)
return;
s->ds = ds;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
io = cpu_register_io_memory(0, led_read, led_write, s);
cpu_register_physical_memory(base, 1, io);
s->console = graphic_console_init(ds, jazz_led_update_display,
jazz_led_invalidate_display,
jazz_led_screen_dump,
jazz_led_text_update, s);
qemu_console_resize(s->console, 60, 80);
s->ds = graphic_console_init(jazz_led_update_display,
jazz_led_invalidate_display,
jazz_led_screen_dump,
jazz_led_text_update, s);
qemu_console_resize(s->ds, 60, 80);
}

8
hw/mainstone.c
View File

@ -69,7 +69,7 @@ static struct arm_boot_info mainstone_binfo = {
};
static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
@ -91,7 +91,7 @@ static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
exit(1);
}
cpu = pxa270_init(mainstone_binfo.ram_size, ds, cpu_model);
cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
cpu_register_physical_memory(0, MAINSTONE_ROM,
qemu_ram_alloc(MAINSTONE_ROM) | IO_MEM_ROM);
@ -135,11 +135,11 @@ static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
}
static void mainstone_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
mainstone_common_init(ram_size, vga_ram_size, ds, kernel_filename,
mainstone_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
}

2
hw/mcf5208.c
View File

@ -198,7 +198,7 @@ static void mcf5208_sys_init(qemu_irq *pic)
}
static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{

5
hw/mips.h
View File

@ -10,15 +10,14 @@ void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
void ds1225y_set_protection(void *opaque, int protection);
/* g364fb.c */
int g364fb_mm_init(DisplayState *ds,
int vram_size, int it_shift,
int g364fb_mm_init(int vram_size, int it_shift,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base);
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
/* jazz_led.c */
extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
extern void jazz_led_init(target_phys_addr_t base);
/* mips_int.c */
extern void cpu_mips_irq_init_cpu(CPUState *env);

16
hw/mips_jazz.c
View File

@ -125,7 +125,7 @@ static void audio_init(qemu_irq *pic)
static
void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *cpu_model,
const char *cpu_model,
enum jazz_model_e jazz_model)
{
char buf[1024];
@ -201,10 +201,10 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
g364fb_mm_init(ds, vga_ram_size, 0, 0x40000000, 0x60000000);
g364fb_mm_init(vga_ram_size, 0, 0x40000000, 0x60000000);
break;
case JAZZ_PICA61:
isa_vga_mm_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size,
isa_vga_mm_init(phys_ram_base + ram_size, ram_size, vga_ram_size,
0x40000000, 0x60000000, 0);
break;
default:
@ -267,25 +267,25 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
ds1225y_init(0x80009000, "nvram");
/* LED indicator */
jazz_led_init(ds, 0x8000f000);
jazz_led_init(0x8000f000);
}
static
void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_MAGNUM);
mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_MAGNUM);
}
static
void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_PICA61);
mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_PICA61);
}
QEMUMachine mips_magnum_machine = {

4
hw/mips_malta.c
View File

@ -763,7 +763,7 @@ static void main_cpu_reset(void *opaque)
static
void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -938,7 +938,7 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
network_init(pci_bus);
/* Optional PCI video card */
pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size,
pci_cirrus_vga_init(pci_bus, phys_ram_base + ram_size,
ram_size, vga_ram_size);
}

2
hw/mips_mipssim.c
View File

@ -108,7 +108,7 @@ static void main_cpu_reset(void *opaque)
static void
mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{

4
hw/mips_r4k.c
View File

@ -148,7 +148,7 @@ static void main_cpu_reset(void *opaque)
static const int sector_len = 32 * 1024;
static
void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -244,7 +244,7 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
}
}
isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
isa_vga_init(phys_ram_base + ram_size, ram_size,
vga_ram_size);
if (nd_table[0].vlan)

14
hw/musicpal.c
View File

@ -752,7 +752,6 @@ typedef struct musicpal_lcd_state {
int page;
int page_off;
DisplayState *ds;
QEMUConsole *console;
uint8_t video_ram[128*64/8];
} musicpal_lcd_state;
@ -906,7 +905,7 @@ static CPUWriteMemoryFunc *musicpal_lcd_writefn[] = {
musicpal_lcd_write
};
static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
static void musicpal_lcd_init(uint32_t base)
{
musicpal_lcd_state *s;
int iomemtype;
@ -914,14 +913,13 @@ static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
s = qemu_mallocz(sizeof(musicpal_lcd_state));
if (!s)
return;
s->ds = ds;
iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
musicpal_lcd_writefn, s);
cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
s->console = graphic_console_init(ds, lcd_refresh, lcd_invalidate,
NULL, NULL, s);
qemu_console_resize(s->console, 128*3, 64*3);
s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
NULL, NULL, s);
qemu_console_resize(s->ds, 128*3, 64*3);
}
/* PIC register offsets */
@ -1404,7 +1402,7 @@ static struct arm_boot_info musicpal_binfo = {
};
static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -1470,7 +1468,7 @@ static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
}
mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
musicpal_lcd_init(ds, MP_LCD_BASE);
musicpal_lcd_init(MP_LCD_BASE);
qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);

19
hw/nseries.c
View File

@ -714,9 +714,9 @@ static void n800_dss_init(struct rfbi_chip_s *chip)
free(fb_blank);
}
static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds)
static void n8x0_dss_setup(struct n800_s *s)
{
s->blizzard.opaque = s1d13745_init(0, ds);
s->blizzard.opaque = s1d13745_init(0);
s->blizzard.block = s1d13745_write_block;
s->blizzard.write = s1d13745_write;
s->blizzard.read = s1d13745_read;
@ -1266,13 +1266,14 @@ static int n810_atag_setup(struct arm_boot_info *info, void *p)
}
static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
DisplayState *ds, const char *kernel_filename,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, struct arm_boot_info *binfo, int model)
{
struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
int sdram_size = binfo->ram_size;
int onenandram_size = 0x00010000;
DisplayState *ds = get_displaystate();
if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
fprintf(stderr, "This architecture uses %i bytes of memory\n",
@ -1280,7 +1281,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
exit(1);
}
s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model);
s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
/* Setup peripherals
*
@ -1317,7 +1318,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
n810_kbd_setup(s);
}
n8x0_spi_setup(s);
n8x0_dss_setup(s, ds);
n8x0_dss_setup(s);
n8x0_cbus_setup(s);
n8x0_uart_setup(s);
if (usb_enabled)
@ -1384,21 +1385,21 @@ static struct arm_boot_info n810_binfo = {
};
static void n800_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
return n8x0_init(ram_size, boot_device, ds,
return n8x0_init(ram_size, boot_device,
kernel_filename, kernel_cmdline, initrd_filename,
cpu_model, &n800_binfo, 800);
}
static void n810_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
return n8x0_init(ram_size, boot_device, ds,
return n8x0_init(ram_size, boot_device,
kernel_filename, kernel_cmdline, initrd_filename,
cpu_model, &n810_binfo, 810);
}

8
hw/omap.h
View File

@ -746,7 +746,7 @@ struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
/* omap_dss.c */
@ -759,7 +759,7 @@ struct rfbi_chip_s {
struct omap_dss_s;
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
target_phys_addr_t l3_base, DisplayState *ds,
target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2);
@ -956,11 +956,11 @@ struct omap_mpu_state_s {
/* omap1.c */
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
DisplayState *ds, const char *core);
const char *core);
/* omap2.c */
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
DisplayState *ds, const char *core);
const char *core);
# if TARGET_PHYS_ADDR_BITS == 32
# define OMAP_FMT_plx "%#08x"

4
hw/omap1.c
View File

@ -4622,7 +4622,7 @@ static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
}
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
DisplayState *ds, const char *core)
const char *core)
{
int i;
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
@ -4704,7 +4704,7 @@ struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
omap_findclk(s, "clk32-kHz"));
s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base,
omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
omap_findclk(s, "lcd_ck"));
omap_ulpd_pm_init(0xfffe0800, s);

4
hw/omap2.c
View File

@ -4492,7 +4492,7 @@ static const struct dma_irq_map omap2_dma_irq_map[] = {
};
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
DisplayState *ds, const char *core)
const char *core)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
@ -4670,7 +4670,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
omap_findclk(s, "spi2_fclk"),
omap_findclk(s, "spi2_iclk"));
s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds,
s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
/* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),

8
hw/omap_dss.c
View File

@ -1022,7 +1022,7 @@ static CPUWriteMemoryFunc *omap_im3_writefn[] = {
};
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
target_phys_addr_t l3_base, DisplayState *ds,
target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
@ -1033,7 +1033,6 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
s->irq = irq;
s->drq = drq;
s->state = ds;
omap_dss_reset(s);
iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn,
@ -1053,9 +1052,8 @@ struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]);
#if 0
if (ds)
graphic_console_init(ds, omap_update_display,
omap_invalidate_display, omap_screen_dump, s);
s->state = graphic_console_init(omap_update_display,
omap_invalidate_display, omap_screen_dump, s);
#endif
return s;

12
hw/omap_lcdc.c
View File

@ -24,7 +24,6 @@
struct omap_lcd_panel_s {
qemu_irq irq;
DisplayState *state;
QEMUConsole *console;
ram_addr_t imif_base;
ram_addr_t emiff_base;
@ -174,7 +173,7 @@ static void omap_update_display(void *opaque)
width = omap_lcd->width;
if (width != ds_get_width(omap_lcd->state) ||
omap_lcd->height != ds_get_height(omap_lcd->state)) {
qemu_console_resize(omap_lcd->console,
qemu_console_resize(omap_lcd->state,
omap_lcd->width, omap_lcd->height);
omap_lcd->invalidate = 1;
}
@ -472,7 +471,7 @@ void omap_lcdc_reset(struct omap_lcd_panel_s *s)
}
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
{
int iomemtype;
@ -481,7 +480,6 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
s->irq = irq;
s->dma = dma;
s->state = ds;
s->imif_base = imif_base;
s->emiff_base = emiff_base;
omap_lcdc_reset(s);
@ -490,9 +488,9 @@ struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
omap_lcdc_writefn, s);
cpu_register_physical_memory(base, 0x100, iomemtype);
s->console = graphic_console_init(ds, omap_update_display,
omap_invalidate_display,
omap_screen_dump, NULL, s);
s->state = graphic_console_init(omap_update_display,
omap_invalidate_display,
omap_screen_dump, NULL, s);
return s;
}

5
hw/omap_sx1.c
View File

@ -136,7 +136,7 @@ static void sx1_init(ram_addr_t ram_size, int vga_ram_size,
flash_size = flash2_size;
}
cpu = omap310_mpu_init(sx1_binfo.ram_size, ds, cpu_model);
cpu = omap310_mpu_init(sx1_binfo.ram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
@ -201,8 +201,7 @@ static void sx1_init(ram_addr_t ram_size, int vga_ram_size,
cpu->env->regs[15] = 0x00000000;
}
ds->surface = qemu_resize_displaysurface(ds->surface, 640, 480, 32, 4 * 640);
dpy_resize(ds);
qemu_console_resize(ds, 640, 480);
}
static void sx1_init_v1(ram_addr_t ram_size, int vga_ram_size,

5
hw/palm.c
View File

@ -200,7 +200,7 @@ static struct arm_boot_info palmte_binfo = {
};
static void palmte_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -214,6 +214,7 @@ static void palmte_init(ram_addr_t ram_size, int vga_ram_size,
static uint32_t cs3val = 0xe1a0e1a0;
ram_addr_t phys_flash;
int rom_size, rom_loaded = 0;
DisplayState *ds = get_displaystate();
if (ram_size < flash_size + sdram_size + OMAP15XX_SRAM_SIZE) {
fprintf(stderr, "This architecture uses %i bytes of memory\n",
@ -221,7 +222,7 @@ static void palmte_init(ram_addr_t ram_size, int vga_ram_size,
exit(1);
}
cpu = omap310_mpu_init(sdram_size, ds, cpu_model);
cpu = omap310_mpu_init(sdram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,

20
hw/pc.c
View File

@ -752,7 +752,7 @@ static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
/* PC hardware initialisation */
static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename,
int pci_enabled, const char *cpu_model)
@ -946,24 +946,24 @@ vga_bios_error:
if (cirrus_vga_enabled) {
if (pci_enabled) {
pci_cirrus_vga_init(pci_bus,
ds, phys_ram_base + vga_ram_addr,
phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
} else {
isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
}
} else if (vmsvga_enabled) {
if (pci_enabled)
pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
else
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
} else if (std_vga_enabled) {
if (pci_enabled) {
pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size, 0, 0);
} else {
isa_vga_init(ds, phys_ram_base + vga_ram_addr,
isa_vga_init(phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
}
}
@ -1111,25 +1111,25 @@ vga_bios_error:
}
static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
pc_init1(ram_size, vga_ram_size, boot_device, ds,
pc_init1(ram_size, vga_ram_size, boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, 1, cpu_model);
}
static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
pc_init1(ram_size, vga_ram_size, boot_device, ds,
pc_init1(ram_size, vga_ram_size, boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, 0, cpu_model);
}

10
hw/pc.h
View File

@ -132,20 +132,20 @@ extern enum vga_retrace_method vga_retrace_method;
#define VGA_RAM_SIZE (9 * 1024 * 1024)
#endif
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
int isa_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
unsigned long vga_bios_offset, int vga_bios_size);
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
int isa_vga_mm_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
int it_shift);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size);
void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
void isa_cirrus_vga_init(uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size);
/* ide.c */

2
hw/pci.h
View File

@ -135,7 +135,7 @@ void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
void *lsi_scsi_init(PCIBus *bus, int devfn);
/* vmware_vga.c */
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
/* usb-uhci.c */

15
hw/pl110.c
View File

@ -29,7 +29,6 @@ enum pl110_bppmode
typedef struct {
DisplayState *ds;
QEMUConsole *console;
/* The Versatile/PB uses a slightly modified PL110 controller. */
int versatile;
@ -271,7 +270,7 @@ static void pl110_resize(pl110_state *s, int width, int height)
{
if (width != s->cols || height != s->rows) {
if (pl110_enabled(s)) {
qemu_console_resize(s->console, width, height);
qemu_console_resize(s->ds, width, height);
}
}
s->cols = width;
@ -386,7 +385,7 @@ static void pl110_write(void *opaque, target_phys_addr_t offset,
s->cr = val;
s->bpp = (val >> 1) & 7;
if (pl110_enabled(s)) {
qemu_console_resize(s->console, s->cols, s->rows);
qemu_console_resize(s->ds, s->cols, s->rows);
}
break;
case 10: /* LCDICR */
@ -410,8 +409,7 @@ static CPUWriteMemoryFunc *pl110_writefn[] = {
pl110_write
};
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq,
int versatile)
void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
{
pl110_state *s;
int iomemtype;
@ -420,12 +418,11 @@ void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq,
iomemtype = cpu_register_io_memory(0, pl110_readfn,
pl110_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
s->ds = ds;
s->versatile = versatile;
s->irq = irq;
s->console = graphic_console_init(ds, pl110_update_display,
pl110_invalidate_display,
NULL, NULL, s);
s->ds = graphic_console_init(pl110_update_display,
pl110_invalidate_display,
NULL, NULL, s);
/* ??? Save/restore. */
return s;
}

4
hw/ppc405_boards.c
View File

@ -172,7 +172,7 @@ static void ref405ep_fpga_init (uint32_t base)
}
static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
@ -496,7 +496,7 @@ static void taihu_cpld_init (uint32_t base)
}
static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,

4
hw/ppc_chrp.c
View File

@ -59,7 +59,7 @@ static CPUReadMemoryFunc *unin_read[] = {
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
@ -256,7 +256,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
pci_bus = pci_pmac_init(pic);
/* init basic PC hardware */
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
pci_vga_init(pci_bus, phys_ram_base + ram_size,
ram_size, vga_ram_size,
vga_bios_offset, vga_bios_size);

4
hw/ppc_oldworld.c
View File

@ -108,7 +108,7 @@ static int vga_osi_call (CPUState *env)
}
static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
@ -297,7 +297,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
}
pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
pci_bus = pci_grackle_init(0xfec00000, pic);
pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size,
vga_bios_offset, vga_bios_size);

4
hw/ppc_prep.c
View File

@ -531,7 +531,7 @@ static CPUReadMemoryFunc *PPC_prep_io_read[] = {
/* PowerPC PREP hardware initialisation */
static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
@ -655,7 +655,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
/* init basic PC hardware */
pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
pci_vga_init(pci_bus, phys_ram_base + ram_size, ram_size,
vga_ram_size, 0, 0);
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
// pit = pit_init(0x40, i8259[0]);

2
hw/primecell.h
View File

@ -9,7 +9,7 @@
void pl031_init(uint32_t base, qemu_irq irq);
/* pl110.c */
void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
void *pl110_init(uint32_t base, qemu_irq irq, int);
/* pl011.c */
enum pl011_type {

7
hw/pxa.h
View File

@ -89,7 +89,7 @@ void pxa2xx_dma_request(struct pxa2xx_dma_state_s *s, int req_num, int on);
/* pxa2xx_lcd.c */
struct pxa2xx_lcdc_s;
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
qemu_irq irq, DisplayState *ds);
qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
@ -215,9 +215,8 @@ struct pxa2xx_i2s_s {
# define PA_FMT "0x%08lx"
# define REG_FMT "0x" TARGET_FMT_plx
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds,
const char *revision);
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds);
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision);
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size);
/* usb-ohci.c */
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,

12
hw/pxa2xx.c
View File

@ -2010,8 +2010,7 @@ static void pxa2xx_reset(void *opaque, int line, int level)
}
/* Initialise a PXA270 integrated chip (ARM based core). */
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
DisplayState *ds, const char *revision)
struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision)
{
struct pxa2xx_state_s *s;
struct pxa2xx_ssp_s *ssp;
@ -2067,8 +2066,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
if (ds)
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
@ -2141,8 +2139,7 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
}
/* Initialise a PXA255 integrated chip (ARM based core). */
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
DisplayState *ds)
struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size)
{
struct pxa2xx_state_s *s;
struct pxa2xx_ssp_s *ssp;
@ -2191,8 +2188,7 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
if (ds)
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */

15
hw/pxa2xx_lcd.c
View File

@ -22,7 +22,6 @@ struct pxa2xx_lcdc_s {
int invalidated;
DisplayState *ds;
QEMUConsole *console;
drawfn *line_fn[2];
int dest_width;
int xres, yres;
@ -792,9 +791,9 @@ static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
if (width != s->xres || height != s->yres) {
if (s->orientation)
qemu_console_resize(s->console, height, width);
qemu_console_resize(s->ds, height, width);
else
qemu_console_resize(s->console, width, height);
qemu_console_resize(s->ds, width, height);
s->invalidated = 1;
s->xres = width;
s->yres = height;
@ -981,8 +980,7 @@ static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
#define BITS 32
#include "pxa2xx_template.h"
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
DisplayState *ds)
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
{
int iomemtype;
struct pxa2xx_lcdc_s *s;
@ -990,7 +988,6 @@ struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
s->invalidated = 1;
s->irq = irq;
s->ds = ds;
pxa2xx_lcdc_orientation(s, graphic_rotate);
@ -998,9 +995,9 @@ struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
pxa2xx_lcdc_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
s->console = graphic_console_init(ds, pxa2xx_update_display,
pxa2xx_invalidate_display,
pxa2xx_screen_dump, NULL, s);
s->ds = graphic_console_init(pxa2xx_update_display,
pxa2xx_invalidate_display,
pxa2xx_screen_dump, NULL, s);
switch (ds_get_bits_per_pixel(s->ds)) {
case 0:

4
hw/r2d.c
View File

@ -193,7 +193,7 @@ static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
}
static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState * ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -222,7 +222,7 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
sm501_vga_ram_addr = qemu_ram_alloc(SM501_VRAM_SIZE);
sm501_init(ds, 0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
sm501_init(0x10000000, sm501_vga_ram_addr, SM501_VRAM_SIZE,
serial_hds[2]);
/* onboard CF (True IDE mode, Master only). */

4
hw/realview.c
View File

@ -24,7 +24,7 @@ static struct arm_boot_info realview_binfo = {
};
static void realview_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -93,7 +93,7 @@ static void realview_init(ram_addr_t ram_size, int vga_ram_size,
sp804_init(0x10011000, pic[4]);
sp804_init(0x10012000, pic[5]);
pl110_init(ds, 0x10020000, pic[23], 1);
pl110_init(0x10020000, pic[23], 1);
index = drive_get_index(IF_SD, 0, 0);
if (index == -1) {

2
hw/shix.c
View File

@ -61,7 +61,7 @@ void vga_screen_dump(const char *filename)
}
static void shix_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState * ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{

10
hw/sm501.c
View File

@ -450,7 +450,6 @@ static const uint32_t sm501_mem_local_size[] = {
typedef struct SM501State {
/* graphic console status */
DisplayState *ds;
QEMUConsole *console;
/* status & internal resources */
target_phys_addr_t base;
@ -994,7 +993,7 @@ static void sm501_draw_crt(SM501State * s)
/* adjust console size */
if (s->last_width != width || s->last_height != height) {
qemu_console_resize(s->console, width, height);
qemu_console_resize(s->ds, width, height);
s->last_width = width;
s->last_height = height;
full_update = 1;
@ -1051,7 +1050,7 @@ static void sm501_update_display(void *opaque)
sm501_draw_crt(s);
}
void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
void sm501_init(uint32_t base, unsigned long local_mem_base,
uint32_t local_mem_bytes, CharDriverState *chr)
{
SM501State * s;
@ -1069,7 +1068,6 @@ void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
s->misc_control = 0x00001000; /* assumes SH, active=low */
s->dc_panel_control = 0x00010000;
s->dc_crt_control = 0x00010000;
s->ds = ds;
/* allocate local memory */
s->local_mem = (uint8 *)phys_ram_base + local_mem_base;
@ -1093,6 +1091,6 @@ void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
115200, chr, 1);
/* create qemu graphic console */
s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
NULL, NULL, s);
s->ds = graphic_console_init(sm501_update_display, NULL,
NULL, NULL, s);
}

20
hw/spitz.c
View File

@ -908,7 +908,7 @@ static struct arm_boot_info spitz_binfo = {
};
static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
DisplayState *ds, const char *kernel_filename,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum spitz_model_e model, int arm_id)
{
@ -924,7 +924,7 @@ static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE);
exit(1);
}
cpu = pxa270_init(spitz_binfo.ram_size, ds, cpu_model);
cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
@ -969,38 +969,38 @@ static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
}
static void spitz_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
}
static void borzoi_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
}
static void akita_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
}
static void terrier_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
}

12
hw/ssd0303.c
View File

@ -45,7 +45,6 @@ enum ssd0303_cmd {
typedef struct {
i2c_slave i2c;
DisplayState *ds;
QEMUConsole *console;
int row;
int col;
int start_line;
@ -306,18 +305,17 @@ static int ssd0303_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address)
void ssd0303_init(i2c_bus *bus, int address)
{
ssd0303_state *s;
s = (ssd0303_state *)i2c_slave_init(bus, address, sizeof(ssd0303_state));
s->ds = ds;
s->i2c.event = ssd0303_event;
s->i2c.recv = ssd0303_recv;
s->i2c.send = ssd0303_send;
s->console = graphic_console_init(ds, ssd0303_update_display,
ssd0303_invalidate_display,
NULL, NULL, s);
qemu_console_resize(s->console, 96 * MAGNIFY, 16 * MAGNIFY);
s->ds = graphic_console_init(ssd0303_update_display,
ssd0303_invalidate_display,
NULL, NULL, s);
qemu_console_resize(s->ds, 96 * MAGNIFY, 16 * MAGNIFY);
register_savevm("ssd0303_oled", -1, 1, ssd0303_save, ssd0303_load, s);
}

12
hw/ssd0323.c
View File

@ -44,7 +44,6 @@ enum ssd0323_mode
typedef struct {
DisplayState *ds;
QEMUConsole *console;
int cmd_len;
int cmd;
@ -322,7 +321,7 @@ static int ssd0323_load(QEMUFile *f, void *opaque, int version_id)
return 0;
}
void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p)
void *ssd0323_init(qemu_irq *cmd_p)
{
ssd0323_state *s;
qemu_irq *cmd;
@ -330,11 +329,10 @@ void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p)
s = (ssd0323_state *)qemu_mallocz(sizeof(ssd0323_state));
s->col_end = 63;
s->row_end = 79;
s->ds = ds;
s->console = graphic_console_init(ds, ssd0323_update_display,
ssd0323_invalidate_display,
NULL, NULL, s);
qemu_console_resize(s->console, 128 * MAGNIFY, 64 * MAGNIFY);
s->ds = graphic_console_init(ssd0323_update_display,
ssd0323_invalidate_display,
NULL, NULL, s);
qemu_console_resize(s->ds, 128 * MAGNIFY, 64 * MAGNIFY);
cmd = qemu_allocate_irqs(ssd0323_cd, s, 1);
*cmd_p = *cmd;

14
hw/stellaris.c
View File

@ -1282,7 +1282,7 @@ static stellaris_board_info stellaris_boards[] = {
};
static void stellaris_init(const char *kernel_filename, const char *cpu_model,
DisplayState *ds, stellaris_board_info *board)
stellaris_board_info *board)
{
static const int uart_irq[] = {5, 6, 33, 34};
static const int timer_irq[] = {19, 21, 23, 35};
@ -1329,7 +1329,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
i2c = i2c_init_bus();
stellaris_i2c_init(0x40020000, pic[8], i2c);
if (board->peripherals & BP_OLED_I2C) {
ssd0303_init(ds, i2c, 0x3d);
ssd0303_init(i2c, 0x3d);
}
}
@ -1346,7 +1346,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
void *ssi_bus;
int index;
oled = ssd0323_init(ds, &gpio_out[GPIO_C][7]);
oled = ssd0323_init(&gpio_out[GPIO_C][7]);
index = drive_get_index(IF_SD, 0, 0);
sd = ssi_sd_init(drives_table[index].bdrv);
@ -1379,19 +1379,19 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
/* FIXME: Figure out how to generate these from stellaris_boards. */
static void lm3s811evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
}
static void lm3s6965evb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[1]);
stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
}
QEMUMachine lm3s811evb_machine = {

60
hw/sun4m.c
View File

@ -423,7 +423,7 @@ static unsigned long sun4m_load_kernel(const char *kernel_filename,
static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
DisplayState *ds, const char *kernel_filename,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
@ -533,7 +533,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
exit (1);
}
tcx_offset = qemu_ram_alloc(hwdef->vram_size);
tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
@ -978,92 +978,92 @@ static const struct sun4m_hwdef sun4m_hwdefs[] = {
/* SPARCstation 5 hardware initialisation */
static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation 10 hardware initialisation */
static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCserver 600MP hardware initialisation */
static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation 20 hardware initialisation */
static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation Voyager hardware initialisation */
static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation LX hardware initialisation */
static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCstation 4 hardware initialisation */
static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCClassic hardware initialisation */
static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCbook hardware initialisation */
static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
@ -1224,7 +1224,7 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
DisplayState *ds, const char *kernel_filename,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -1316,7 +1316,7 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
exit (1);
}
tcx_offset = qemu_ram_alloc(hwdef->vram_size);
tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
@ -1366,21 +1366,21 @@ static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
/* SPARCserver 1000 hardware initialisation */
static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCcenter 2000 hardware initialisation */
static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
@ -1439,7 +1439,7 @@ static const struct sun4c_hwdef sun4c_hwdefs[] = {
static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
DisplayState *ds, const char *kernel_filename,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -1522,7 +1522,7 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
exit (1);
}
tcx_offset = qemu_ram_alloc(hwdef->vram_size);
tcx_init(ds, hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
@ -1584,11 +1584,11 @@ static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
/* SPARCstation 2 hardware initialisation */
static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}

2
hw/sun4m.h
View File

@ -22,7 +22,7 @@ static inline void sparc_iommu_memory_write(void *opaque,
}
/* tcx.c */
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
unsigned long vram_offset, int vram_size, int width, int height,
int depth);

16
hw/sun4u.c
View File

@ -387,7 +387,7 @@ pci_ebus_init(PCIBus *bus, int devfn)
}
static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_devices, DisplayState *ds,
const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
const struct hwdef *hwdef)
@ -508,7 +508,7 @@ static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
&pci_bus3);
isa_mem_base = VGA_BASE;
vga_ram_offset = qemu_ram_alloc(vga_ram_size);
pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_offset,
pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
vga_ram_offset, vga_ram_size,
0, 0);
@ -612,31 +612,31 @@ static const struct hwdef hwdefs[] = {
/* Sun4u hardware initialisation */
static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_devices, DisplayState *ds,
const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
}
/* Sun4v hardware initialisation */
static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_devices, DisplayState *ds,
const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
}
/* Niagara hardware initialisation */
static void niagara_init(ram_addr_t RAM_size, int vga_ram_size,
const char *boot_devices, DisplayState *ds,
const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
}

27
hw/tc6393xb.c
View File

@ -122,7 +122,6 @@ struct tc6393xb_s {
struct ecc_state_s ecc;
DisplayState *ds;
QEMUConsole *console;
ram_addr_t vram_addr;
uint32_t scr_width, scr_height; /* in pixels */
qemu_irq l3v;
@ -485,7 +484,7 @@ static void tc6393xb_update_display(void *opaque)
full_update = 1;
}
if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
qemu_console_resize(s->console, s->scr_width, s->scr_height);
qemu_console_resize(s->ds, s->scr_width, s->scr_height);
full_update = 1;
}
if (s->blanked)
@ -563,7 +562,7 @@ static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t valu
tc6393xb_writeb(opaque, addr + 3, value >> 24);
}
struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq, DisplayState *ds)
struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq)
{
int iomemtype;
struct tc6393xb_s *s;
@ -593,19 +592,15 @@ struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq, DisplayState *ds)
tc6393xb_writefn, s);
cpu_register_physical_memory(base, 0x10000, iomemtype);
if (ds) {
s->ds = ds;
s->vram_addr = qemu_ram_alloc(0x100000);
cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr);
s->scr_width = 480;
s->scr_height = 640;
s->console = graphic_console_init(ds,
tc6393xb_update_display,
NULL, /* invalidate */
NULL, /* screen_dump */
NULL, /* text_update */
s);
}
s->vram_addr = qemu_ram_alloc(0x100000);
cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr);
s->scr_width = 480;
s->scr_height = 640;
s->ds = graphic_console_init(tc6393xb_update_display,
NULL, /* invalidate */
NULL, /* screen_dump */
NULL, /* text_update */
s);
return s;
}

18
hw/tcx.c
View File

@ -36,7 +36,6 @@
typedef struct TCXState {
target_phys_addr_t addr;
DisplayState *ds;
QEMUConsole *console;
uint8_t *vram;
uint32_t *vram24, *cplane;
ram_addr_t vram_offset, vram24_offset, cplane_offset;
@ -491,7 +490,7 @@ static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
tcx_dummy_writel,
};
void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
unsigned long vram_offset, int vram_size, int width, int height,
int depth)
{
@ -502,7 +501,6 @@ void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
s = qemu_mallocz(sizeof(TCXState));
if (!s)
return;
s->ds = ds;
s->addr = addr;
s->vram_offset = vram_offset;
s->width = width;
@ -538,15 +536,15 @@ void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
s->cplane = (uint32_t *)vram_base;
s->cplane_offset = vram_offset;
cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
s->console = graphic_console_init(s->ds, tcx24_update_display,
tcx24_invalidate_display,
tcx24_screen_dump, NULL, s);
s->ds = graphic_console_init(tcx24_update_display,
tcx24_invalidate_display,
tcx24_screen_dump, NULL, s);
} else {
cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
dummy_memory);
s->console = graphic_console_init(s->ds, tcx_update_display,
tcx_invalidate_display,
tcx_screen_dump, NULL, s);
s->ds = graphic_console_init(tcx_update_display,
tcx_invalidate_display,
tcx_screen_dump, NULL, s);
}
// NetBSD writes here even with 8-bit display
cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
@ -555,7 +553,7 @@ void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
qemu_register_reset(tcx_reset, s);
tcx_reset(s);
qemu_console_resize(s->console, width, height);
qemu_console_resize(s->ds, width, height);
}
static void tcx_screen_dump(void *opaque, const char *filename)

7
hw/tosa.c
View File

@ -197,7 +197,7 @@ static struct arm_boot_info tosa_binfo = {
};
static void tosa_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
@ -214,14 +214,13 @@ static void tosa_init(ram_addr_t ram_size, int vga_ram_size,
if (!cpu_model)
cpu_model = "pxa255";
cpu = pxa255_init(tosa_binfo.ram_size, NULL);
cpu = pxa255_init(tosa_binfo.ram_size);
cpu_register_physical_memory(0, TOSA_ROM,
qemu_ram_alloc(TOSA_ROM) | IO_MEM_ROM);
tmio = tc6393xb_init(0x10000000,
pxa2xx_gpio_in_get(cpu->gpio)[TOSA_GPIO_TC6393XB_INT],
ds);
pxa2xx_gpio_in_get(cpu->gpio)[TOSA_GPIO_TC6393XB_INT]);
scp0 = scoop_init(cpu, 0, 0x08800000);
scp1 = scoop_init(cpu, 1, 0x14800040);

12
hw/versatilepb.c
View File

@ -156,7 +156,7 @@ static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
static struct arm_boot_info versatile_binfo;
static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
int board_id)
@ -228,7 +228,7 @@ static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
/* The versatile/PB actually has a modified Color LCD controller
that includes hardware cursor support from the PL111. */
pl110_init(ds, 0x10120000, pic[16], 1);
pl110_init(0x10120000, pic[16], 1);
index = drive_get_index(IF_SD, 0, 0);
if (index == -1) {
@ -290,23 +290,23 @@ static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
}
static void vpb_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
versatile_init(ram_size, vga_ram_size,
boot_device, ds,
boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 0x183);
}
static void vab_init(ram_addr_t ram_size, int vga_ram_size,
const char *boot_device, DisplayState *ds,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
versatile_init(ram_size, vga_ram_size,
boot_device, ds,
boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 0x25e);
}

33
hw/vga.c
View File

@ -1307,7 +1307,7 @@ static void vga_draw_text(VGAState *s, int full_update)
cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
s->last_scr_width = width * cw;
s->last_scr_height = height * cheight;
qemu_console_resize(s->console, s->last_scr_width, s->last_scr_height);
qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
s->last_depth = 0;
s->last_width = width;
s->last_height = height;
@ -1682,10 +1682,10 @@ static void vga_draw_graphic(VGAState *s, int full_update)
s->vram_ptr + (s->start_addr * 4));
dpy_resize(s->ds);
} else {
qemu_console_resize(s->console, disp_width, height);
qemu_console_resize(s->ds, disp_width, height);
}
} else {
qemu_console_resize(s->console, disp_width, height);
qemu_console_resize(s->ds, disp_width, height);
}
s->last_scr_width = disp_width;
s->last_scr_height = height;
@ -2254,7 +2254,7 @@ static void vga_map(PCIDevice *pci_dev, int region_num,
vga_dirty_log_start(s);
}
void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size)
{
int i, j, v, b;
@ -2285,7 +2285,6 @@ void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
s->vram_ptr = vga_ram_base;
s->vram_offset = vga_ram_offset;
s->vram_size = vga_ram_size;
s->ds = ds;
s->get_bpp = vga_get_bpp;
s->get_offsets = vga_get_offsets;
s->get_resolution = vga_get_resolution;
@ -2434,7 +2433,7 @@ static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
}
int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
int isa_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
VGAState *s;
@ -2443,11 +2442,11 @@ int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
if (!s)
return -1;
vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init(s);
s->console = graphic_console_init(s->ds, s->update, s->invalidate,
s->screen_dump, s->text_update, s);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
@ -2457,7 +2456,7 @@ int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
return 0;
}
int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
int isa_vga_mm_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
int it_shift)
@ -2468,11 +2467,11 @@ int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
if (!s)
return -1;
vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_mm_init(s, vram_base, ctrl_base, it_shift);
s->console = graphic_console_init(s->ds, s->update, s->invalidate,
s->screen_dump, s->text_update, s);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
@ -2482,7 +2481,7 @@ int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
return 0;
}
int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
unsigned long vga_bios_offset, int vga_bios_size)
{
@ -2497,11 +2496,11 @@ int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
return -1;
s = &d->vga_state;
vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init(s);
s->console = graphic_console_init(s->ds, s->update, s->invalidate,
s->screen_dump, s->text_update, s);
s->ds = graphic_console_init(s->update, s->invalidate,
s->screen_dump, s->text_update, s);
s->pci_dev = &d->dev;

3
hw/vga_int.h
View File

@ -145,7 +145,6 @@ typedef void (* vga_update_retrace_info_fn)(struct VGAState *s);
VGA_STATE_COMMON_BOCHS_VBE \
/* display refresh support */ \
DisplayState *ds; \
QEMUConsole *console; \
uint32_t font_offsets[2]; \
int graphic_mode; \
uint8_t shift_control; \
@ -192,7 +191,7 @@ static inline int c6_to_8(int v)
return (v << 2) | (b << 1) | b;
}
void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
ram_addr_t vga_ram_offset, int vga_ram_size);
void vga_init(VGAState *s);
void vga_reset(void *s);

24
hw/vmware_vga.c
View File

@ -57,7 +57,6 @@ struct vmsvga_state_s {
#ifndef EMBED_STDVGA
DisplayState *ds;
QEMUConsole *console;
int vram_size;
ram_addr_t vram_offset;
#endif
@ -384,7 +383,7 @@ static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
# ifdef DIRECT_VRAM
if (s->ds->dpy_copy)
qemu_console_copy(s->console, x0, y0, x1, y1, w, h);
qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
else
# endif
{
@ -877,7 +876,7 @@ static inline void vmsvga_size(struct vmsvga_state_s *s)
if (s->new_width != s->width || s->new_height != s->height) {
s->width = s->new_width;
s->height = s->new_height;
qemu_console_resize(s->console, s->width, s->height);
qemu_console_resize(s->ds, s->width, s->height);
s->invalidated = 1;
}
}
@ -915,7 +914,7 @@ static void vmsvga_reset(struct vmsvga_state_s *s)
s->width = -1;
s->height = -1;
s->svgaid = SVGA_ID;
s->depth = ds_get_bits_per_pixel(s->ds) ? ds_get_bits_per_pixel(s->ds) : 24;
s->depth = 24;
s->bypp = (s->depth + 7) >> 3;
s->cursor.on = 0;
s->redraw_fifo_first = 0;
@ -1110,11 +1109,10 @@ static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
return 0;
}
static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
static void vmsvga_init(struct vmsvga_state_s *s,
uint8_t *vga_ram_base, unsigned long vga_ram_offset,
int vga_ram_size)
{
s->ds = ds;
s->vram = vga_ram_base;
s->vram_size = vga_ram_size;
s->vram_offset = vga_ram_offset;
@ -1125,15 +1123,15 @@ static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
vmsvga_reset(s);
#ifdef EMBED_STDVGA
vga_common_init((VGAState *) s, ds,
vga_common_init((VGAState *) s,
vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init((VGAState *) s);
#endif
s->console = graphic_console_init(ds, vmsvga_update_display,
vmsvga_invalidate_display,
vmsvga_screen_dump,
vmsvga_text_update, s);
s->ds = graphic_console_init(vmsvga_update_display,
vmsvga_invalidate_display,
vmsvga_screen_dump,
vmsvga_text_update, s);
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
@ -1213,7 +1211,7 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
#define PCI_CLASS_SUB_VGA 0x00
#define PCI_CLASS_HEADERTYPE_00h 0x00
void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
struct pci_vmsvga_state_s *s;
@ -1243,7 +1241,7 @@ void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
pci_register_io_region(&s->card, 1, vga_ram_size,
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
vmsvga_init(&s->chip, vga_ram_base, vga_ram_offset, vga_ram_size);
register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
}

4
qemu-char.c
View File

@ -2128,10 +2128,10 @@ CharDriverState *qemu_chr_open(const char *label, const char *filename)
CharDriverState *chr;
if (!strcmp(filename, "vc")) {
chr = text_console_init(&display_state, 0);
chr = text_console_init(get_displaystate(), 0);
} else
if (strstart(filename, "vc:", &p)) {
chr = text_console_init(&display_state, p);
chr = text_console_init(get_displaystate(), p);
} else
if (!strcmp(filename, "null")) {
chr = qemu_chr_open_null();

1
sysemu.h
View File

@ -101,7 +101,6 @@ extern int no_quit;
extern int semihosting_enabled;
extern int old_param;
extern const char *bootp_filename;
extern DisplayState display_state;
#ifdef USE_KQEMU
extern int kqemu_allowed;

144
vl.c
View File

@ -187,7 +187,7 @@ DriveInfo drives_table[MAX_DRIVES+1];
int nb_drives;
static int vga_ram_size;
enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;
DisplayState display_state;
static DisplayState *display_state;
int nographic;
static int curses;
static int sdl;
@ -2756,6 +2756,23 @@ void pcmcia_info(void)
}
/***********************************************************/
/* register display */
void register_displaystate(DisplayState *ds)
{
DisplayState **s;
s = &display_state;
while (*s != NULL)
s = &(*s)->next;
ds->next = NULL;
*s = ds;
}
DisplayState *get_displaystate(void)
{
return display_state;
}
/* dumb display */
static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
@ -4502,7 +4519,7 @@ int main(int argc, char **argv, char **envp)
const char *initrd_filename;
const char *kernel_filename, *kernel_cmdline;
const char *boot_devices = "";
DisplayState *ds = &display_state;
DisplayState *ds;
DisplayChangeListener *dcl;
int cyls, heads, secs, translation;
const char *net_clients[MAX_NET_CLIENTS];
@ -5414,9 +5431,63 @@ int main(int argc, char **argv, char **envp)
register_savevm("timer", 0, 2, timer_save, timer_load, NULL);
register_savevm_live("ram", 0, 3, ram_save_live, NULL, ram_load, NULL);
#ifndef _WIN32
/* must be after terminal init, SDL library changes signal handlers */
termsig_setup();
#endif
/* Maintain compatibility with multiple stdio monitors */
if (!strcmp(monitor_device,"stdio")) {
for (i = 0; i < MAX_SERIAL_PORTS; i++) {
const char *devname = serial_devices[i];
if (devname && !strcmp(devname,"mon:stdio")) {
monitor_device = NULL;
break;
} else if (devname && !strcmp(devname,"stdio")) {
monitor_device = NULL;
serial_devices[i] = "mon:stdio";
break;
}
}
}
if (kvm_enabled()) {
int ret;
ret = kvm_init(smp_cpus);
if (ret < 0) {
fprintf(stderr, "failed to initialize KVM\n");
exit(1);
}
}
machine->init(ram_size, vga_ram_size, boot_devices,
kernel_filename, kernel_cmdline, initrd_filename, cpu_model);
/* Set KVM's vcpu state to qemu's initial CPUState. */
if (kvm_enabled()) {
int ret;
ret = kvm_sync_vcpus();
if (ret < 0) {
fprintf(stderr, "failed to initialize vcpus\n");
exit(1);
}
}
/* init USB devices */
if (usb_enabled) {
for(i = 0; i < usb_devices_index; i++) {
if (usb_device_add(usb_devices[i]) < 0) {
fprintf(stderr, "Warning: could not add USB device %s\n",
usb_devices[i]);
}
}
}
/* just use the first displaystate for the moment */
ds = display_state;
/* terminal init */
memset(&display_state, 0, sizeof(display_state));
ds->surface = qemu_create_displaysurface(640, 480, 32, 640 * 4);
if (nographic) {
if (curses) {
fprintf(stderr, "fatal: -nographic can't be used with -curses\n");
@ -5448,25 +5519,16 @@ int main(int argc, char **argv, char **envp)
}
}
dpy_resize(ds);
#ifndef _WIN32
/* must be after terminal init, SDL library changes signal handlers */
termsig_setup();
#endif
/* Maintain compatibility with multiple stdio monitors */
if (!strcmp(monitor_device,"stdio")) {
for (i = 0; i < MAX_SERIAL_PORTS; i++) {
const char *devname = serial_devices[i];
if (devname && !strcmp(devname,"mon:stdio")) {
monitor_device = NULL;
break;
} else if (devname && !strcmp(devname,"stdio")) {
monitor_device = NULL;
serial_devices[i] = "mon:stdio";
break;
}
dcl = ds->listeners;
while (dcl != NULL) {
if (dcl->dpy_refresh != NULL) {
ds->gui_timer = qemu_new_timer(rt_clock, gui_update, ds);
qemu_mod_timer(ds->gui_timer, qemu_get_clock(rt_clock));
}
dcl = dcl->next;
}
if (monitor_device) {
monitor_hd = qemu_chr_open("monitor", monitor_device);
if (!monitor_hd) {
@ -5524,48 +5586,6 @@ int main(int argc, char **argv, char **envp)
}
}
if (kvm_enabled()) {
int ret;
ret = kvm_init(smp_cpus);
if (ret < 0) {
fprintf(stderr, "failed to initialize KVM\n");
exit(1);
}
}
machine->init(ram_size, vga_ram_size, boot_devices, ds,
kernel_filename, kernel_cmdline, initrd_filename, cpu_model);
/* Set KVM's vcpu state to qemu's initial CPUState. */
if (kvm_enabled()) {
int ret;
ret = kvm_sync_vcpus();
if (ret < 0) {
fprintf(stderr, "failed to initialize vcpus\n");
exit(1);
}
}
/* init USB devices */
if (usb_enabled) {
for(i = 0; i < usb_devices_index; i++) {
if (usb_device_add(usb_devices[i]) < 0) {
fprintf(stderr, "Warning: could not add USB device %s\n",
usb_devices[i]);
}
}
}
dcl = ds->listeners;
while (dcl != NULL) {
if (dcl->dpy_refresh != NULL) {
display_state.gui_timer = qemu_new_timer(rt_clock, gui_update, &display_state);
qemu_mod_timer(display_state.gui_timer, qemu_get_clock(rt_clock));
}
dcl = dcl->next;
}
#ifdef CONFIG_GDBSTUB
if (use_gdbstub) {
/* XXX: use standard host:port notation and modify options