Add lxvd2x
This patch adds the lxvd2x instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
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@ -7003,6 +7003,22 @@ static inline TCGv_i64 cpu_vsrl(int n)
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}
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}
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}
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}
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static void gen_lxvd2x(DisasContext *ctx)
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{
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TCGv EA;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
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tcg_gen_addi_tl(EA, EA, 8);
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gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
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tcg_temp_free(EA);
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}
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/*** SPE extension ***/
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/*** SPE extension ***/
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/* Register moves */
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/* Register moves */
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@ -9452,6 +9468,8 @@ GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
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GEN_VAFORM_PAIRED(vsel, vperm, 21),
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GEN_VAFORM_PAIRED(vsel, vperm, 21),
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GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
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GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
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GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
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#undef GEN_SPE
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#undef GEN_SPE
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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#define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
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