target/nios2: Split mmu_write
Create three separate functions for the three separate registers. Avoid extra dispatch through op_helper.c. Dispatch to the correct function in translation. Clean up the ifdefs in wrctl. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -21,6 +21,8 @@
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DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
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#if !defined(CONFIG_USER_ONLY)
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DEF_HELPER_3(mmu_write, void, env, i32, i32)
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DEF_HELPER_2(mmu_write_tlbacc, void, env, i32)
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DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32)
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DEF_HELPER_2(mmu_write_pteaddr, void, env, i32)
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DEF_HELPER_1(check_interrupts, void, env)
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#endif
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@ -23,6 +23,7 @@
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "mmu.h"
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#include "exec/helper-proto.h"
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#include "trace/trace-target_nios2.h"
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@ -80,106 +81,103 @@ static void mmu_flush_pid(CPUNios2State *env, uint32_t pid)
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}
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}
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void mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
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{
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CPUState *cs = env_cpu(env);
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Nios2CPU *cpu = env_archcpu(env);
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switch (rn) {
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case CR_TLBACC:
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trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT,
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(v & CR_TLBACC_C) ? 'C' : '.',
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(v & CR_TLBACC_R) ? 'R' : '.',
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(v & CR_TLBACC_W) ? 'W' : '.',
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(v & CR_TLBACC_X) ? 'X' : '.',
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(v & CR_TLBACC_G) ? 'G' : '.',
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v & CR_TLBACC_PFN_MASK);
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trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT,
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(v & CR_TLBACC_C) ? 'C' : '.',
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(v & CR_TLBACC_R) ? 'R' : '.',
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(v & CR_TLBACC_W) ? 'W' : '.',
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(v & CR_TLBACC_X) ? 'X' : '.',
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(v & CR_TLBACC_G) ? 'G' : '.',
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v & CR_TLBACC_PFN_MASK);
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/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
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if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
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int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
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int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int g = (v & CR_TLBACC_G) ? 1 : 0;
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int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid;
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uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W |
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CR_TLBACC_X | CR_TLBACC_PFN_MASK);
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/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
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if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) {
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int way = (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
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int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
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int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
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int g = (v & CR_TLBACC_G) ? 1 : 0;
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int valid = ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0;
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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uint32_t newTag = (vpn << 12) | (g << 11) | (valid << 10) | pid;
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uint32_t newData = v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W |
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CR_TLBACC_X | CR_TLBACC_PFN_MASK);
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if ((entry->tag != newTag) || (entry->data != newData)) {
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if (entry->tag & (1 << 10)) {
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/* Flush existing entry */
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tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
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}
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entry->tag = newTag;
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entry->data = newData;
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if ((entry->tag != newTag) || (entry->data != newData)) {
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if (entry->tag & (1 << 10)) {
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/* Flush existing entry */
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tlb_flush_page(cs, entry->tag & TARGET_PAGE_MASK);
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}
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/* Auto-increment tlbmisc.WAY */
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env->regs[CR_TLBMISC] =
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(env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
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(((way + 1) & (cpu->tlb_num_ways - 1)) <<
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CR_TLBMISC_WAY_SHIFT);
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entry->tag = newTag;
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entry->data = newData;
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}
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/* Writes to TLBACC don't change the read-back value */
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env->mmu.tlbacc_wr = v;
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break;
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case CR_TLBMISC:
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trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
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(v & CR_TLBMISC_RD) ? 'R' : '.',
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(v & CR_TLBMISC_WR) ? 'W' : '.',
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(v & CR_TLBMISC_DBL) ? '2' : '.',
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(v & CR_TLBMISC_BAD) ? 'B' : '.',
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(v & CR_TLBMISC_PERM) ? 'P' : '.',
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(v & CR_TLBMISC_D) ? 'D' : '.',
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(v & CR_TLBMISC_PID_MASK) >> 4);
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if ((v & CR_TLBMISC_PID_MASK) !=
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(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
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mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
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CR_TLBMISC_PID_SHIFT);
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}
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/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
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if (v & CR_TLBMISC_RD) {
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int way = (v >> CR_TLBMISC_WAY_SHIFT);
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int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
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env->regs[CR_TLBACC] |= entry->data;
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env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
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env->regs[CR_TLBMISC] =
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(v & ~CR_TLBMISC_PID_MASK) |
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
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CR_TLBMISC_PID_SHIFT);
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env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
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env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
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} else {
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env->regs[CR_TLBMISC] = v;
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}
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env->mmu.tlbmisc_wr = v;
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break;
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case CR_PTEADDR:
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trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT,
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(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT);
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/* Writes to PTEADDR don't change the read-back VPN value */
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env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
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(env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK);
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env->mmu.pteaddr_wr = v;
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break;
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default:
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break;
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/* Auto-increment tlbmisc.WAY */
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env->regs[CR_TLBMISC] =
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(env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
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(((way + 1) & (cpu->tlb_num_ways - 1)) <<
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CR_TLBMISC_WAY_SHIFT);
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}
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/* Writes to TLBACC don't change the read-back value */
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env->mmu.tlbacc_wr = v;
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}
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void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
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{
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Nios2CPU *cpu = env_archcpu(env);
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trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
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(v & CR_TLBMISC_RD) ? 'R' : '.',
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(v & CR_TLBMISC_WR) ? 'W' : '.',
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(v & CR_TLBMISC_DBL) ? '2' : '.',
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(v & CR_TLBMISC_BAD) ? 'B' : '.',
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(v & CR_TLBMISC_PERM) ? 'P' : '.',
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(v & CR_TLBMISC_D) ? 'D' : '.',
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(v & CR_TLBMISC_PID_MASK) >> 4);
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if ((v & CR_TLBMISC_PID_MASK) !=
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(env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
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mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
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CR_TLBMISC_PID_SHIFT);
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}
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/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
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if (v & CR_TLBMISC_RD) {
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int way = (v >> CR_TLBMISC_WAY_SHIFT);
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int vpn = (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2;
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Nios2TLBEntry *entry =
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&env->mmu.tlb[(way * cpu->tlb_num_ways) +
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(vpn & env->mmu.tlb_entry_mask)];
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env->regs[CR_TLBACC] &= CR_TLBACC_IGN_MASK;
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env->regs[CR_TLBACC] |= entry->data;
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env->regs[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
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env->regs[CR_TLBMISC] =
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(v & ~CR_TLBMISC_PID_MASK) |
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((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
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CR_TLBMISC_PID_SHIFT);
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env->regs[CR_PTEADDR] &= ~CR_PTEADDR_VPN_MASK;
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env->regs[CR_PTEADDR] |= (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT;
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} else {
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env->regs[CR_TLBMISC] = v;
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}
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env->mmu.tlbmisc_wr = v;
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}
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void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v)
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{
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trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT,
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(v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_VPN_SHIFT);
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/* Writes to PTEADDR don't change the read-back VPN value */
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env->regs[CR_PTEADDR] = (v & ~CR_PTEADDR_VPN_MASK) |
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(env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK);
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env->mmu.pteaddr_wr = v;
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}
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void mmu_init(CPUNios2State *env)
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@ -26,11 +26,6 @@
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#include "qemu/main-loop.h"
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#if !defined(CONFIG_USER_ONLY)
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void helper_mmu_write(CPUNios2State *env, uint32_t rn, uint32_t v)
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{
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mmu_write(env, rn, v);
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}
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static void nios2_check_interrupts(CPUNios2State *env)
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{
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if (env->irq_pending &&
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@ -461,30 +461,28 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
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/* ctlN <- rA */
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static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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R_TYPE(instr, code);
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gen_check_supervisor(dc);
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#ifndef CONFIG_USER_ONLY
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R_TYPE(instr, code);
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TCGv v = load_gpr(dc, instr.a);
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switch (instr.imm5 + CR_BASE) {
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case CR_PTEADDR:
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case CR_TLBACC:
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case CR_TLBMISC:
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{
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#if !defined(CONFIG_USER_ONLY)
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TCGv_i32 tmp = tcg_const_i32(instr.imm5 + CR_BASE);
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gen_helper_mmu_write(cpu_env, tmp, load_gpr(dc, instr.a));
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tcg_temp_free_i32(tmp);
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#endif
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gen_helper_mmu_write_pteaddr(cpu_env, v);
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break;
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case CR_TLBACC:
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gen_helper_mmu_write_tlbacc(cpu_env, v);
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break;
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case CR_TLBMISC:
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gen_helper_mmu_write_tlbmisc(cpu_env, v);
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break;
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}
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default:
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tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], load_gpr(dc, instr.a));
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tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
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break;
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}
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/* If interrupts were enabled using WRCTL, trigger them. */
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#if !defined(CONFIG_USER_ONLY)
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if ((instr.imm5 + CR_BASE) == CR_STATUS) {
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if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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