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target-arm: support thumb exception handlers

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When handling an exception, switch to the correct mode based on the
Thumb Exception (TE) bit in the SCTLR.

Signed-off-by: Rabin Vincent <rabin@rab.in>
This commit is contained in:
Rabin Vincent 2010-02-15 00:02:36 +05:30 committed by Paul Brook
parent b8b45b68f8
commit 30a8cac139
1 changed files with 2 additions and 3 deletions
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5
target-arm/helper.c
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@ -824,11 +824,10 @@ void do_interrupt(CPUARMState *env)
env->spsr = cpsr_read(env); env->spsr = cpsr_read(env);
/* Clear IT bits. */ /* Clear IT bits. */
env->condexec_bits = 0; env->condexec_bits = 0;
/* Switch to the new mode, and switch to Arm mode. */ /* Switch to the new mode, and to the correct instruction set. */
/* ??? Thumb interrupt handlers not implemented. */
env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
env->uncached_cpsr |= mask; env->uncached_cpsr |= mask;
env->thumb = 0; env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
env->regs[14] = env->regs[15] + offset; env->regs[14] = env->regs[15] + offset;
env->regs[15] = addr; env->regs[15] = addr;
env->interrupt_request |= CPU_INTERRUPT_EXITTB; env->interrupt_request |= CPU_INTERRUPT_EXITTB;