OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/riscv: add support for Zcf extension

Browse Source 
Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230307081403.61950-4-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-07 16:13:56 +08:00 committed by Alistair Francis
parent b17dd74a54
commit 30b0357902
2 changed files with 22 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
target/riscv/insn16.decode
View File

@ -109,11 +109,11 @@ sw 110 ... ... .. ... 00 @cs_w
# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
{
ld 011 ... ... .. ... 00 @cl_d
flw 011 ... ... .. ... 00 @cl_w
c_flw 011 ... ... .. ... 00 @cl_w
}
{
sd 111 ... ... .. ... 00 @cs_d
fsw 111 ... ... .. ... 00 @cs_w
c_fsw 111 ... ... .. ... 00 @cs_w
}
# *** RV32/64C Standard Extension (Quadrant 1) ***
@ -174,9 +174,9 @@ sw 110 . ..... ..... 10 @c_swsp
{
c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
ld 011 . ..... ..... 10 @c_ldsp
flw 011 . ..... ..... 10 @c_lwsp
c_flw 011 . ..... ..... 10 @c_lwsp
}
{
sd 111 . ..... ..... 10 @c_sdsp
fsw 111 . ..... ..... 10 @c_swsp
c_fsw 111 . ..... ..... 10 @c_swsp
}

18
target/riscv/insn_trans/trans_rvf.c.inc
View File

@ -30,6 +30,12 @@
} \
} while (0)
#define REQUIRE_ZCF(ctx) do { \
if (!ctx->cfg_ptr->ext_zcf) { \
return false; \
} \
} while (0)
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
TCGv_i64 dest;
@ -61,6 +67,18 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
return true;
}
static bool trans_c_flw(DisasContext *ctx, arg_flw *a)
{
REQUIRE_ZCF(ctx);
return trans_flw(ctx, a);
}
static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a)
{
REQUIRE_ZCF(ctx);
return trans_fsw(ctx, a);
}
static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a)
{
REQUIRE_FPU;