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i.MX: Add implementation of i.MX7 GPR IP block 

Add minimal code needed to allow upstream Linux guest to boot.

Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Marcel Apfelbaum <marcel.apfelbaum@zoho.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Cc: yurovsky@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrey Smirnov 2018-02-09 10:40:30 +00:00 committed by Peter Maydell
parent a62bf59fd9
commit 30b2f8709d
4 changed files with 157 additions and 0 deletions
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1
hw/misc/Makefile.objs
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@ -36,6 +36,7 @@ obj-$(CONFIG_IMX) += imx6_src.o
obj-$(CONFIG_IMX) += imx7_ccm.o
obj-$(CONFIG_IMX) += imx2_wdt.o
obj-$(CONFIG_IMX) += imx7_snvs.o
obj-$(CONFIG_IMX) += imx7_gpr.o
obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o
obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o
obj-$(CONFIG_MAINSTONE) += mst_fpga.o

124
hw/misc/imx7_gpr.c Normal file
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@ -0,0 +1,124 @@
/*
* Copyright (c) 2018, Impinj, Inc.
*
* i.MX7 GPR IP block emulation code
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*
* Bare minimum emulation code needed to support being able to shut
* down linux guest gracefully.
*/
#include "qemu/osdep.h"
#include "hw/misc/imx7_gpr.h"
#include "qemu/log.h"
#include "sysemu/sysemu.h"
#include "trace.h"
enum IMX7GPRRegisters {
IOMUXC_GPR0 = 0x00,
IOMUXC_GPR1 = 0x04,
IOMUXC_GPR2 = 0x08,
IOMUXC_GPR3 = 0x0c,
IOMUXC_GPR4 = 0x10,
IOMUXC_GPR5 = 0x14,
IOMUXC_GPR6 = 0x18,
IOMUXC_GPR7 = 0x1c,
IOMUXC_GPR8 = 0x20,
IOMUXC_GPR9 = 0x24,
IOMUXC_GPR10 = 0x28,
IOMUXC_GPR11 = 0x2c,
IOMUXC_GPR12 = 0x30,
IOMUXC_GPR13 = 0x34,
IOMUXC_GPR14 = 0x38,
IOMUXC_GPR15 = 0x3c,
IOMUXC_GPR16 = 0x40,
IOMUXC_GPR17 = 0x44,
IOMUXC_GPR18 = 0x48,
IOMUXC_GPR19 = 0x4c,
IOMUXC_GPR20 = 0x50,
IOMUXC_GPR21 = 0x54,
IOMUXC_GPR22 = 0x58,
};
#define IMX7D_GPR1_IRQ_MASK BIT(12)
#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK BIT(13)
#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK BIT(14)
#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
#define IMX7D_GPR1_ENET1_CLK_DIR_MASK BIT(17)
#define IMX7D_GPR1_ENET2_CLK_DIR_MASK BIT(18)
#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI BIT(4)
#define IMX7D_GPR12_PCIE_PHY_REFCLK_SEL BIT(5)
#define IMX7D_GPR22_PCIE_PHY_PLL_LOCKED BIT(31)
static uint64_t imx7_gpr_read(void *opaque, hwaddr offset, unsigned size)
{
trace_imx7_gpr_read(offset);
if (offset == IOMUXC_GPR22) {
return IMX7D_GPR22_PCIE_PHY_PLL_LOCKED;
}
return 0;
}
static void imx7_gpr_write(void *opaque, hwaddr offset,
uint64_t v, unsigned size)
{
trace_imx7_gpr_write(offset, v);
}
static const struct MemoryRegionOps imx7_gpr_ops = {
.read = imx7_gpr_read,
.write = imx7_gpr_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.impl = {
/*
* Our device would not work correctly if the guest was doing
* unaligned access. This might not be a limitation on the
* real device but in practice there is no reason for a guest
* to access this device unaligned.
*/
.min_access_size = 4,
.max_access_size = 4,
.unaligned = false,
},
};
static void imx7_gpr_init(Object *obj)
{
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
IMX7GPRState *s = IMX7_GPR(obj);
memory_region_init_io(&s->mmio, obj, &imx7_gpr_ops, s,
TYPE_IMX7_GPR, 64 * 1024);
sysbus_init_mmio(sd, &s->mmio);
}
static void imx7_gpr_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "i.MX7 General Purpose Registers Module";
}
static const TypeInfo imx7_gpr_info = {
.name = TYPE_IMX7_GPR,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IMX7GPRState),
.instance_init = imx7_gpr_init,
.class_init = imx7_gpr_class_init,
};
static void imx7_gpr_register_type(void)
{
type_register_static(&imx7_gpr_info);
}
type_init(imx7_gpr_register_type)

4
hw/misc/trace-events
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@ -66,3 +66,7 @@ mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) "MPS2 SCC
msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) "msf2-sysreg write: addr 0x%08" HWADDR_PRIx " data 0x%" PRIx32 " prev 0x%" PRIx32
msf2_sysreg_read(uint64_t offset, uint32_t val) "msf2-sysreg read: addr 0x%08" HWADDR_PRIx " data 0x%08" PRIx32
msf2_sysreg_write_pll_status(void) "Invalid write to read only PLL status register"
#hw/misc/imx7_gpr.c
imx7_gpr_read(uint64_t offset) "addr 0x%08" HWADDR_PRIx
imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" HWADDR_PRIx "value 0x%08" HWADDR_PRIx

28
include/hw/misc/imx7_gpr.h Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2017, Impinj, Inc.
*
* i.MX7 GPR IP block emulation code
*
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef IMX7_GPR_H
#define IMX7_GPR_H
#include "qemu/bitops.h"
#include "hw/sysbus.h"
#define TYPE_IMX7_GPR "imx7.gpr"
#define IMX7_GPR(obj) OBJECT_CHECK(IMX7GPRState, (obj), TYPE_IMX7_GPR)
typedef struct IMX7GPRState {
/* <private> */
SysBusDevice parent_obj;
MemoryRegion mmio;
} IMX7GPRState;
#endif /* IMX7_GPR_H */