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target/ppc: moved XXSPLTW to using decodetree 

Changed the function that handles XXSPLTW emulation to using decodetree,
but still using the same logic.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20211104123719.323713-19-matheus.ferst@eldorado.org.br>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Bruno Larsen (billionai) 2021-11-04 09:37:12 -03:00 committed by David Gibson
parent dcbf48316f
commit 30dfca8d8f
3 changed files with 15 additions and 12 deletions
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9
target/ppc/insn32.decode
View File

@ -116,6 +116,11 @@
&X_vrt_frbp vrt frbp
@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
&XX2 xt xb uim:uint8_t
%xx2_xt 0:1 21:5
%xx2_xb 1:1 11:5
@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
&Z22_bf_fra bf fra dm
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
@ -406,3 +411,7 @@ LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
## VSX splat instruction
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2

17
target/ppc/translate/vsx-impl.c.inc
View File

@ -1436,26 +1436,21 @@ static void gen_xxsel(DisasContext *ctx)
vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
}
static void gen_xxspltw(DisasContext *ctx)
static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
{
int rt = xT(ctx->opcode);
int rb = xB(ctx->opcode);
int uim = UIM(ctx->opcode);
int tofs, bofs;
if (unlikely(!ctx->vsx_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
REQUIRE_VSX(ctx);
tofs = vsr_full_offset(rt);
bofs = vsr_full_offset(rb);
bofs += uim << MO_32;
tofs = vsr_full_offset(a->xt);
bofs = vsr_full_offset(a->xb);
bofs += a->uim << MO_32;
#ifndef HOST_WORDS_BIG_ENDIAN
bofs ^= 8 | 4;
#endif
tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
return true;
}
#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))

1
target/ppc/translate/vsx-ops.c.inc
View File

@ -348,7 +348,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),