target/ppc: moved XXSPLTW to using decodetree
Changed the function that handles XXSPLTW emulation to using decodetree, but still using the same logic. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-19-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -116,6 +116,11 @@
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&X_vrt_frbp vrt frbp
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&X_vrt_frbp vrt frbp
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@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
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@X_vrt_frbp ...... vrt:5 ..... ....0 .......... . &X_vrt_frbp frbp=%x_frbp
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&XX2 xt xb uim:uint8_t
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%xx2_xt 0:1 21:5
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%xx2_xb 1:1 11:5
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@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx2_xt xb=%xx2_xb
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&Z22_bf_fra bf fra dm
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&Z22_bf_fra bf fra dm
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@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
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@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
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@ -406,3 +411,7 @@ LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
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STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
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STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
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LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
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LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
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STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
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STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
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## VSX splat instruction
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XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
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@ -1436,26 +1436,21 @@ static void gen_xxsel(DisasContext *ctx)
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vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
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vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
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}
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}
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static void gen_xxspltw(DisasContext *ctx)
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static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
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{
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{
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int rt = xT(ctx->opcode);
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int rb = xB(ctx->opcode);
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int uim = UIM(ctx->opcode);
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int tofs, bofs;
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int tofs, bofs;
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if (unlikely(!ctx->vsx_enabled)) {
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REQUIRE_VSX(ctx);
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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tofs = vsr_full_offset(rt);
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tofs = vsr_full_offset(a->xt);
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bofs = vsr_full_offset(rb);
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bofs = vsr_full_offset(a->xb);
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bofs += uim << MO_32;
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bofs += a->uim << MO_32;
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#ifndef HOST_WORDS_BIG_ENDIAN
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#ifndef HOST_WORDS_BIG_ENDIAN
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bofs ^= 8 | 4;
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bofs ^= 8 | 4;
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#endif
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#endif
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tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
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tcg_gen_gvec_dup_mem(MO_32, tofs, bofs, 16, 16);
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return true;
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}
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}
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#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
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#define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff))
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@ -348,7 +348,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
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GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
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GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
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GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
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GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
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GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
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GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
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GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
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GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
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GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
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GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
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GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
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GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
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GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
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