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target/riscv: Only support little endian guests 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com
Message-Id: <93e5d4f13eca0d2a588e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis 2020-08-12 12:13:41 -07:00
parent f8dc878efc
commit 30f663b16f
1 changed files with 5 additions and 0 deletions
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5
target/riscv/csr.c
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@ -840,6 +840,8 @@ static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
#endif
/* We only support little endian */
*val = set_field(*val, HSTATUS_VSBE, 0);
return 0;
}
@ -851,6 +853,9 @@ static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
}
#endif
if (get_field(val, HSTATUS_VSBE) != 0) {
qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
}
return 0;
}