target-sh4: minor optimisations
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno
parent
37cc0b44b4
commit
3101e99c21
@ -664,7 +664,7 @@ static void _decode_opc(DisasContext * ctx)
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TCGv addr = tcg_temp_new();
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tcg_gen_subi_i32(addr, REG(B11_8), 1);
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tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); /* modify register status */
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tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
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tcg_temp_free(addr);
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}
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return;
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@ -673,7 +673,7 @@ static void _decode_opc(DisasContext * ctx)
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TCGv addr = tcg_temp_new();
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tcg_gen_subi_i32(addr, REG(B11_8), 2);
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tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 2);
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tcg_gen_mov_i32(REG(B11_8), addr);
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tcg_temp_free(addr);
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}
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return;
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@ -682,7 +682,7 @@ static void _decode_opc(DisasContext * ctx)
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TCGv addr = tcg_temp_new();
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
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tcg_gen_mov_i32(REG(B11_8), addr);
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}
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return;
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case 0x6004: /* mov.b @Rm+,Rn */
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@ -750,17 +750,13 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0x6008: /* swap.b Rm,Rn */
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{
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TCGv highw, high, low;
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highw = tcg_temp_new();
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tcg_gen_andi_i32(highw, REG(B7_4), 0xffff0000);
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TCGv high, low;
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high = tcg_temp_new();
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tcg_gen_ext8u_i32(high, REG(B7_4));
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tcg_gen_shli_i32(high, high, 8);
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tcg_gen_andi_i32(high, REG(B7_4), 0xffff0000);
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low = tcg_temp_new();
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tcg_gen_shri_i32(low, REG(B7_4), 8);
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tcg_gen_ext8u_i32(low, low);
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tcg_gen_ext16u_i32(low, REG(B7_4));
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tcg_gen_bswap16_i32(low, low);
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tcg_gen_or_i32(REG(B11_8), high, low);
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tcg_gen_or_i32(REG(B11_8), REG(B11_8), highw);
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tcg_temp_free(low);
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tcg_temp_free(high);
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}
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@ -769,8 +765,7 @@ static void _decode_opc(DisasContext * ctx)
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{
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TCGv high, low;
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high = tcg_temp_new();
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tcg_gen_ext16u_i32(high, REG(B7_4));
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tcg_gen_shli_i32(high, high, 16);
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tcg_gen_shli_i32(high, REG(B7_4), 16);
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low = tcg_temp_new();
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tcg_gen_shri_i32(low, REG(B7_4), 16);
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tcg_gen_ext16u_i32(low, low);
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@ -783,8 +778,7 @@ static void _decode_opc(DisasContext * ctx)
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{
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TCGv high, low;
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high = tcg_temp_new();
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tcg_gen_ext16u_i32(high, REG(B7_4));
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tcg_gen_shli_i32(high, high, 16);
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tcg_gen_shli_i32(high, REG(B7_4), 16);
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low = tcg_temp_new();
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tcg_gen_shri_i32(low, REG(B11_8), 16);
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tcg_gen_ext16u_i32(low, low);
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@ -974,20 +968,24 @@ static void _decode_opc(DisasContext * ctx)
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int label2 = gen_new_label();
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int label3 = gen_new_label();
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int label4 = gen_new_label();
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TCGv shift = tcg_temp_local_new();
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TCGv shift;
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tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
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/* Rm positive, shift to the left */
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shift = tcg_temp_new();
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tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
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tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
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tcg_temp_free(shift);
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tcg_gen_br(label4);
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/* Rm negative, shift to the right */
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gen_set_label(label1);
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shift = tcg_temp_new();
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tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
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tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
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tcg_gen_not_i32(shift, REG(B7_4));
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tcg_gen_andi_i32(shift, shift, 0x1f);
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tcg_gen_addi_i32(shift, shift, 1);
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tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift);
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tcg_temp_free(shift);
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tcg_gen_br(label4);
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/* Rm = -32 */
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gen_set_label(label2);
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@ -997,7 +995,6 @@ static void _decode_opc(DisasContext * ctx)
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gen_set_label(label3);
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tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
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gen_set_label(label4);
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tcg_temp_free(shift);
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}
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return;
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case 0x400d: /* shld Rm,Rn */
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@ -1005,26 +1002,29 @@ static void _decode_opc(DisasContext * ctx)
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int label1 = gen_new_label();
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int label2 = gen_new_label();
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int label3 = gen_new_label();
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TCGv shift = tcg_temp_local_new();
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TCGv shift;
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tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
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/* Rm positive, shift to the left */
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shift = tcg_temp_new();
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tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
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tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift);
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tcg_temp_free(shift);
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tcg_gen_br(label3);
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/* Rm negative, shift to the right */
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gen_set_label(label1);
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shift = tcg_temp_new();
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tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
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tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
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tcg_gen_not_i32(shift, REG(B7_4));
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tcg_gen_andi_i32(shift, shift, 0x1f);
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tcg_gen_addi_i32(shift, shift, 1);
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tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift);
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tcg_temp_free(shift);
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tcg_gen_br(label3);
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/* Rm = -32 */
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gen_set_label(label2);
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tcg_gen_movi_i32(REG(B11_8), 0);
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gen_set_label(label3);
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tcg_temp_free(shift);
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}
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return;
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case 0x3008: /* sub Rm,Rn */
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@ -1106,7 +1106,7 @@ static void _decode_opc(DisasContext * ctx)
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int fr = XREG(B7_4);
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
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tcg_gen_subi_i32(addr, REG(B11_8), 8);
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tcg_gen_subi_i32(addr, addr, 4);
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tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
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tcg_gen_mov_i32(REG(B11_8), addr);
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tcg_temp_free(addr);
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@ -1115,8 +1115,8 @@ static void _decode_opc(DisasContext * ctx)
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addr = tcg_temp_new_i32();
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx);
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tcg_gen_mov_i32(REG(B11_8), addr);
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tcg_temp_free(addr);
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
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}
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return;
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case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
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@ -1436,8 +1436,8 @@ static void _decode_opc(DisasContext * ctx)
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TCGv addr = tcg_temp_new();
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
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tcg_gen_mov_i32(REG(B11_8), addr);
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tcg_temp_free(addr);
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
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}
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return;
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}
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@ -1505,8 +1505,8 @@ static void _decode_opc(DisasContext * ctx)
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TCGv addr = tcg_temp_new();
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
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tcg_gen_mov_i32(REG(B11_8), addr);
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tcg_temp_free(addr);
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
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}
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return;
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#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
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@ -1526,11 +1526,11 @@ static void _decode_opc(DisasContext * ctx)
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case stpnum: \
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prechk \
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{ \
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TCGv addr = tcg_temp_new(); \
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TCGv addr = tcg_temp_new(); \
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tcg_gen_subi_i32(addr, REG(B11_8), 4); \
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tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
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tcg_gen_mov_i32(REG(B11_8), addr); \
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tcg_temp_free(addr); \
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4); \
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} \
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return;
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LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {})
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@ -1571,9 +1571,9 @@ static void _decode_opc(DisasContext * ctx)
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addr = tcg_temp_new();
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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tcg_gen_qemu_st32(val, addr, ctx->memidx);
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tcg_gen_mov_i32(REG(B11_8), addr);
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tcg_temp_free(addr);
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tcg_temp_free(val);
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tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 4);
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}
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return;
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case 0x00c3: /* movca.l R0,@Rm */
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