Merge patch series "target/riscv: Some updates to float point related extensions"
RISC-V defines a handful of extensions related to floating point, along with various relationships between these and other extensions. This patch set adds support for the Zvfh, Zvhfmin, and Zve64d extensions; along with a handful of fixes and cleanups related to the other floating-point extension relationships. * b4-shazam-merge target/riscv: Expose properties for Zv* extensions target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc target/riscv: Fix check for vector load/store instructions when EEW=64 target/riscv: Add support for Zvfh/zvfhmin extensions target/riscv: Remove rebundunt check for zve32f and zve64f target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc target/riscv: Simplify check for Zve32f and Zve64f target/riscv: Indent fixes in cpu.c target/riscv: Add propertie check for Zvfh{min} extensions target/riscv: Fix relationship between V, Zve*, F and D target/riscv: Add cfg properties for Zv* extensions target/riscv: Simplify the check for Zfhmin and Zhinxmin target/riscv: Fix the relationship between Zhinxmin and Zhinx target/riscv: Fix the relationship between Zfhmin and Zfh Message-ID: <20230215020539.4788-1-liweiwei@iscas.ac.cn> [Palmer: commit text] Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
commit
312f632f4c
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@ -101,6 +101,9 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt),
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ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f),
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ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f),
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ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d),
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ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh),
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ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin),
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ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx),
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ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin),
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ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia),
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@ -729,7 +732,11 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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return;
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}
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if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) {
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if (cpu->cfg.ext_zfh) {
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cpu->cfg.ext_zfhmin = true;
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}
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if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
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error_setg(errp, "Zfh/Zfhmin extensions require F extension");
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return;
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}
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@ -739,19 +746,51 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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return;
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}
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if (cpu->cfg.ext_v && !cpu->cfg.ext_d) {
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error_setg(errp, "V extension requires D extension");
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/* The V vector extension depends on the Zve64d extension */
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if (cpu->cfg.ext_v) {
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cpu->cfg.ext_zve64d = true;
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}
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/* The Zve64d extension depends on the Zve64f extension */
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if (cpu->cfg.ext_zve64d) {
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cpu->cfg.ext_zve64f = true;
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}
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/* The Zve64f extension depends on the Zve32f extension */
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if (cpu->cfg.ext_zve64f) {
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cpu->cfg.ext_zve32f = true;
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}
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if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) {
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error_setg(errp, "Zve64d/V extensions require D extension");
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return;
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}
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if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
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if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
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error_setg(errp, "Zve32f/Zve64f extensions require F extension");
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return;
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}
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if (cpu->cfg.ext_zvfh) {
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cpu->cfg.ext_zvfhmin = true;
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}
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if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
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error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
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return;
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}
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if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
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error_setg(errp, "Zvfh extensions requires Zfhmin extension");
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return;
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}
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/* Set the ISA extensions, checks should have happened above */
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if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx ||
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cpu->cfg.ext_zhinxmin) {
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if (cpu->cfg.ext_zhinx) {
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cpu->cfg.ext_zhinxmin = true;
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}
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if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) {
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cpu->cfg.ext_zfinx = true;
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}
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@ -762,7 +801,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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}
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if (cpu->cfg.ext_f) {
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error_setg(errp,
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"Zfinx cannot be supported together with F extension");
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"Zfinx cannot be supported together with F extension");
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return;
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}
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}
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@ -825,40 +864,40 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
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ext |= RVV;
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if (!is_power_of_2(cpu->cfg.vlen)) {
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error_setg(errp,
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"Vector extension VLEN must be power of 2");
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"Vector extension VLEN must be power of 2");
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return;
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}
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if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
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error_setg(errp,
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"Vector extension implementation only supports VLEN "
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"in the range [128, %d]", RV_VLEN_MAX);
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"Vector extension implementation only supports VLEN "
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"in the range [128, %d]", RV_VLEN_MAX);
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return;
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}
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if (!is_power_of_2(cpu->cfg.elen)) {
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error_setg(errp,
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"Vector extension ELEN must be power of 2");
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"Vector extension ELEN must be power of 2");
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return;
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}
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if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
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error_setg(errp,
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"Vector extension implementation only supports ELEN "
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"in the range [8, 64]");
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return;
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}
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if (cpu->cfg.vext_spec) {
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if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
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vext_version = VEXT_VERSION_1_00_0;
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} else {
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if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
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error_setg(errp,
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"Unsupported vector spec version '%s'",
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cpu->cfg.vext_spec);
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"Vector extension implementation only supports ELEN "
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"in the range [8, 64]");
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return;
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}
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} else {
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qemu_log("vector version is not specified, "
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"use the default value v1.0\n");
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}
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set_vext_version(env, vext_version);
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if (cpu->cfg.vext_spec) {
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if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
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vext_version = VEXT_VERSION_1_00_0;
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} else {
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error_setg(errp,
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"Unsupported vector spec version '%s'",
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cpu->cfg.vext_spec);
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return;
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}
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} else {
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qemu_log("vector version is not specified, "
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"use the default value v1.0\n");
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}
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set_vext_version(env, vext_version);
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}
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if (cpu->cfg.ext_j) {
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ext |= RVJ;
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@ -1079,6 +1118,7 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
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DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
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DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
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DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
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DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
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DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
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DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
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@ -1138,6 +1178,9 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
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DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
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DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
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DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
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DEFINE_PROP_END_OF_LIST(),
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};
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@ -449,7 +449,10 @@ struct RISCVCPUConfig {
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bool ext_zhinxmin;
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bool ext_zve32f;
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bool ext_zve64f;
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bool ext_zve64d;
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bool ext_zmmul;
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bool ext_zvfh;
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bool ext_zvfhmin;
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bool ext_smaia;
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bool ext_ssaia;
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bool ext_sscofpmf;
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@ -51,7 +51,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
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*cs_base = 0;
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if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
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if (cpu->cfg.ext_zve32f) {
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/*
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* If env->vl equals to VLMAX, we can use generic vector operation
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* expanders (GVEC) to accerlate the vector operations.
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@ -93,8 +93,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
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CPUState *cs = env_cpu(env);
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RISCVCPU *cpu = RISCV_CPU(cs);
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if (env->misa_ext & RVV ||
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cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
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if (cpu->cfg.ext_zve32f) {
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#if !defined(CONFIG_USER_ONLY)
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if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
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return RISCV_EXCP_ILLEGAL_INST;
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@ -40,10 +40,11 @@ static bool require_rvf(DisasContext *s)
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switch (s->sew) {
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case MO_16:
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return s->cfg_ptr->ext_zvfh;
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case MO_32:
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return has_ext(s, RVF);
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return s->cfg_ptr->ext_zve32f;
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case MO_64:
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return has_ext(s, RVD);
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return s->cfg_ptr->ext_zve64d;
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default:
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return false;
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}
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@ -57,57 +58,32 @@ static bool require_scale_rvf(DisasContext *s)
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switch (s->sew) {
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case MO_8:
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return s->cfg_ptr->ext_zvfh;
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case MO_16:
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return has_ext(s, RVF);
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return s->cfg_ptr->ext_zve32f;
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case MO_32:
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return has_ext(s, RVD);
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return s->cfg_ptr->ext_zve64d;
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default:
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return false;
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}
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}
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static bool require_zve32f(DisasContext *s)
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static bool require_scale_rvfmin(DisasContext *s)
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{
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/* RVV + Zve32f = RVV. */
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if (has_ext(s, RVV)) {
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return true;
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if (s->mstatus_fs == 0) {
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return false;
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}
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/* Zve32f doesn't support FP64. (Section 18.2) */
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return s->cfg_ptr->ext_zve32f ? s->sew <= MO_32 : true;
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}
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static bool require_scale_zve32f(DisasContext *s)
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{
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/* RVV + Zve32f = RVV. */
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if (has_ext(s, RVV)) {
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return true;
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switch (s->sew) {
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case MO_8:
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return s->cfg_ptr->ext_zvfhmin;
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case MO_16:
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return s->cfg_ptr->ext_zve32f;
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case MO_32:
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return s->cfg_ptr->ext_zve64d;
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default:
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return false;
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}
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/* Zve32f doesn't support FP64. (Section 18.2) */
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return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
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}
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static bool require_zve64f(DisasContext *s)
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{
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/* RVV + Zve64f = RVV. */
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if (has_ext(s, RVV)) {
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return true;
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}
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/* Zve64f doesn't support FP64. (Section 18.2) */
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return s->cfg_ptr->ext_zve64f ? s->sew <= MO_32 : true;
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}
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static bool require_scale_zve64f(DisasContext *s)
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{
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/* RVV + Zve64f = RVV. */
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if (has_ext(s, RVV)) {
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return true;
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}
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/* Zve64f doesn't support FP64. (Section 18.2) */
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return s->cfg_ptr->ext_zve64f ? s->sew <= MO_16 : true;
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}
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/* Destination vector register group cannot overlap source mask register. */
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@ -173,9 +149,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
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{
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TCGv s1, dst;
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if (!require_rvv(s) ||
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!(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
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s->cfg_ptr->ext_zve64f)) {
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if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
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return false;
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}
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@ -210,9 +184,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
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{
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TCGv dst;
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if (!require_rvv(s) ||
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!(has_ext(s, RVV) || s->cfg_ptr->ext_zve32f ||
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s->cfg_ptr->ext_zve64f)) {
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if (!require_rvv(s) || !s->cfg_ptr->ext_zve32f) {
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return false;
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}
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@ -315,13 +287,12 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf,
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require_nf(vd, nf, s->lmul);
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/*
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* All Zve* extensions support all vector load and store instructions,
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* except Zve64* extensions do not support EEW=64 for index values
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* when XLEN=32. (Section 18.2)
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* V extension supports all vector load and store instructions,
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* except V extension does not support EEW=64 for index values
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* when XLEN=32. (Section 18.3)
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*/
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if (get_xl(s) == MXL_RV32) {
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ret &= (!has_ext(s, RVV) &&
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s->cfg_ptr->ext_zve64f ? eew != MO_64 : true);
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ret &= (eew != MO_64);
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}
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return ret;
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@ -2027,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
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* are not included for EEW=64 in Zve64*. (Section 18.2)
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*/
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return opivv_check(s, a) &&
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(!has_ext(s, RVV) &&
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s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
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(!has_ext(s, RVV) ? s->sew != MO_64 : true);
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}
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static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
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|
@ -2041,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
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* are not included for EEW=64 in Zve64*. (Section 18.2)
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*/
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return opivx_check(s, a) &&
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(!has_ext(s, RVV) &&
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s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
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(!has_ext(s, RVV) ? s->sew != MO_64 : true);
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}
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GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
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|
@ -2259,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
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* for EEW=64 in Zve64*. (Section 18.2)
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||||
*/
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||||
return opivv_check(s, a) &&
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(!has_ext(s, RVV) &&
|
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s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
|
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(!has_ext(s, RVV) ? s->sew != MO_64 : true);
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||||
}
|
||||
|
||||
static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
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|
@ -2271,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
|
|||
* for EEW=64 in Zve64*. (Section 18.2)
|
||||
*/
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||||
return opivx_check(s, a) &&
|
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(!has_ext(s, RVV) &&
|
||||
s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
|
||||
(!has_ext(s, RVV) ? s->sew != MO_64 : true);
|
||||
}
|
||||
|
||||
GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
|
||||
|
@ -2335,9 +2302,7 @@ static bool opfvv_check(DisasContext *s, arg_rmrr *a)
|
|||
return require_rvv(s) &&
|
||||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
/* OPFVV without GVEC IR */
|
||||
|
@ -2425,9 +2390,7 @@ static bool opfvf_check(DisasContext *s, arg_rmrr *a)
|
|||
return require_rvv(s) &&
|
||||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_ss(s, a->rd, a->rs2, a->vm) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
vext_check_ss(s, a->rd, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
/* OPFVF without GVEC IR */
|
||||
|
@ -2465,9 +2428,7 @@ static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a)
|
|||
require_scale_rvf(s) &&
|
||||
(s->sew != MO_8) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
/* OPFVV with WIDEN */
|
||||
|
@ -2510,9 +2471,7 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
|
|||
require_scale_rvf(s) &&
|
||||
(s->sew != MO_8) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_ds(s, a->rd, a->rs2, a->vm) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
vext_check_ds(s, a->rd, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
/* OPFVF with WIDEN */
|
||||
|
@ -2544,9 +2503,7 @@ static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
|
|||
require_scale_rvf(s) &&
|
||||
(s->sew != MO_8) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
/* WIDEN OPFVV with WIDEN */
|
||||
|
@ -2589,9 +2546,7 @@ static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a)
|
|||
require_scale_rvf(s) &&
|
||||
(s->sew != MO_8) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_dd(s, a->rd, a->rs2, a->vm) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
vext_check_dd(s, a->rd, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
/* WIDEN OPFVF with WIDEN */
|
||||
|
@ -2668,9 +2623,7 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
|
|||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
/* OPFV instructions ignore vs1 check */
|
||||
vext_check_ss(s, a->rd, a->rs2, a->vm) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
vext_check_ss(s, a->rd, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
static bool do_opfv(DisasContext *s, arg_rmr *a,
|
||||
|
@ -2735,9 +2688,7 @@ static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a)
|
|||
return require_rvv(s) &&
|
||||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_mss(s, a->rd, a->rs1, a->rs2) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
vext_check_mss(s, a->rd, a->rs1, a->rs2);
|
||||
}
|
||||
|
||||
GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check)
|
||||
|
@ -2750,9 +2701,7 @@ static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a)
|
|||
return require_rvv(s) &&
|
||||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
vext_check_ms(s, a->rd, a->rs2) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
vext_check_ms(s, a->rd, a->rs2);
|
||||
}
|
||||
|
||||
GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check)
|
||||
|
@ -2773,9 +2722,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
|
|||
if (require_rvv(s) &&
|
||||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
require_align(a->rd, s->lmul) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s)) {
|
||||
require_align(a->rd, s->lmul)) {
|
||||
gen_set_rm(s, RISCV_FRM_DYN);
|
||||
|
||||
TCGv_i64 t1;
|
||||
|
@ -2860,18 +2807,14 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
|
|||
static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
|
||||
{
|
||||
return opfv_widen_check(s, a) &&
|
||||
require_rvf(s) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
require_rvf(s);
|
||||
}
|
||||
|
||||
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
|
||||
{
|
||||
return opfv_widen_check(s, a) &&
|
||||
require_scale_rvf(s) &&
|
||||
(s->sew != MO_8) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
require_scale_rvfmin(s) &&
|
||||
(s->sew != MO_8);
|
||||
}
|
||||
|
||||
#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \
|
||||
|
@ -2922,9 +2865,7 @@ static bool opfxv_widen_check(DisasContext *s, arg_rmr *a)
|
|||
require_scale_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
/* OPFV widening instructions ignore vs1 check */
|
||||
vext_check_ds(s, a->rd, a->rs2, a->vm) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
vext_check_ds(s, a->rd, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
#define GEN_OPFXV_WIDEN_TRANS(NAME) \
|
||||
|
@ -2979,18 +2920,21 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
|
|||
{
|
||||
return opfv_narrow_check(s, a) &&
|
||||
require_rvf(s) &&
|
||||
(s->sew != MO_64) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
(s->sew != MO_64);
|
||||
}
|
||||
|
||||
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
|
||||
{
|
||||
return opfv_narrow_check(s, a) &&
|
||||
require_scale_rvfmin(s) &&
|
||||
(s->sew != MO_8);
|
||||
}
|
||||
|
||||
static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a)
|
||||
{
|
||||
return opfv_narrow_check(s, a) &&
|
||||
require_scale_rvf(s) &&
|
||||
(s->sew != MO_8) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
(s->sew != MO_8);
|
||||
}
|
||||
|
||||
#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \
|
||||
|
@ -3030,7 +2974,7 @@ GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w,
|
|||
GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
|
||||
RISCV_FRM_DYN)
|
||||
/* Reuse the helper function from vfncvt.f.f.w */
|
||||
GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_narrow_check, vfncvt_f_f_w,
|
||||
GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f_w,
|
||||
RISCV_FRM_ROD)
|
||||
|
||||
static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
|
||||
|
@ -3039,9 +2983,7 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
|
|||
require_scale_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
/* OPFV narrowing instructions ignore vs1 check */
|
||||
vext_check_sd(s, a->rd, a->rs2, a->vm) &&
|
||||
require_scale_zve32f(s) &&
|
||||
require_scale_zve64f(s);
|
||||
vext_check_sd(s, a->rd, a->rs2, a->vm);
|
||||
}
|
||||
|
||||
#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \
|
||||
|
@ -3115,9 +3057,7 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check)
|
|||
static bool freduction_check(DisasContext *s, arg_rmrr *a)
|
||||
{
|
||||
return reduction_check(s, a) &&
|
||||
require_rvf(s) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
require_rvf(s);
|
||||
}
|
||||
|
||||
GEN_OPFVV_TRANS(vfredusum_vs, freduction_check)
|
||||
|
@ -3544,9 +3484,7 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a)
|
|||
{
|
||||
if (require_rvv(s) &&
|
||||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s)) {
|
||||
vext_check_isa_ill(s)) {
|
||||
gen_set_rm(s, RISCV_FRM_DYN);
|
||||
|
||||
unsigned int ofs = (8 << s->sew);
|
||||
|
@ -3572,9 +3510,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
|
|||
{
|
||||
if (require_rvv(s) &&
|
||||
require_rvf(s) &&
|
||||
vext_check_isa_ill(s) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s)) {
|
||||
vext_check_isa_ill(s)) {
|
||||
gen_set_rm(s, RISCV_FRM_DYN);
|
||||
|
||||
/* The instructions ignore LMUL and vector register group. */
|
||||
|
@ -3625,17 +3561,13 @@ GEN_OPIVI_TRANS(vslidedown_vi, IMM_ZX, vslidedown_vx, slidedown_check)
|
|||
static bool fslideup_check(DisasContext *s, arg_rmrr *a)
|
||||
{
|
||||
return slideup_check(s, a) &&
|
||||
require_rvf(s) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
require_rvf(s);
|
||||
}
|
||||
|
||||
static bool fslidedown_check(DisasContext *s, arg_rmrr *a)
|
||||
{
|
||||
return slidedown_check(s, a) &&
|
||||
require_rvf(s) &&
|
||||
require_zve32f(s) &&
|
||||
require_zve64f(s);
|
||||
require_rvf(s);
|
||||
}
|
||||
|
||||
GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check)
|
||||
|
|
|
@ -28,15 +28,14 @@
|
|||
} \
|
||||
} while (0)
|
||||
|
||||
#define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \
|
||||
if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \
|
||||
#define REQUIRE_ZFHMIN(ctx) do { \
|
||||
if (!ctx->cfg_ptr->ext_zfhmin) { \
|
||||
return false; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \
|
||||
if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin || \
|
||||
ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \
|
||||
#define REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx) do { \
|
||||
if (!(ctx->cfg_ptr->ext_zfhmin || ctx->cfg_ptr->ext_zhinxmin)) { \
|
||||
return false; \
|
||||
} \
|
||||
} while (0)
|
||||
|
@ -47,7 +46,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a)
|
|||
TCGv t0;
|
||||
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN(ctx);
|
||||
REQUIRE_ZFHMIN(ctx);
|
||||
|
||||
decode_save_opc(ctx);
|
||||
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
|
||||
|
@ -70,7 +69,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a)
|
|||
TCGv t0;
|
||||
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN(ctx);
|
||||
REQUIRE_ZFHMIN(ctx);
|
||||
|
||||
decode_save_opc(ctx);
|
||||
t0 = get_gpr(ctx, a->rs1, EXT_NONE);
|
||||
|
@ -401,7 +400,7 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a)
|
|||
static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
|
||||
{
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
||||
REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
|
||||
|
||||
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
||||
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
||||
|
@ -418,7 +417,7 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a)
|
|||
static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
|
||||
{
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
||||
REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
|
||||
REQUIRE_ZDINX_OR_D(ctx);
|
||||
|
||||
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
||||
|
@ -436,7 +435,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a)
|
|||
static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
|
||||
{
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
||||
REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
|
||||
|
||||
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
||||
TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1);
|
||||
|
@ -452,7 +451,7 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a)
|
|||
static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a)
|
||||
{
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx);
|
||||
REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx);
|
||||
REQUIRE_ZDINX_OR_D(ctx);
|
||||
|
||||
TCGv_i64 dest = dest_fpr(ctx, a->rd);
|
||||
|
@ -585,7 +584,7 @@ static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a)
|
|||
static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
|
||||
{
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN(ctx);
|
||||
REQUIRE_ZFHMIN(ctx);
|
||||
|
||||
TCGv dest = dest_gpr(ctx, a->rd);
|
||||
|
||||
|
@ -605,7 +604,7 @@ static bool trans_fmv_x_h(DisasContext *ctx, arg_fmv_x_h *a)
|
|||
static bool trans_fmv_h_x(DisasContext *ctx, arg_fmv_h_x *a)
|
||||
{
|
||||
REQUIRE_FPU;
|
||||
REQUIRE_ZFH_OR_ZFHMIN(ctx);
|
||||
REQUIRE_ZFHMIN(ctx);
|
||||
|
||||
TCGv t0 = get_gpr(ctx, a->rs1, EXT_ZERO);
|
||||
|
||||
|
|
Loading…
Reference in New Issue