hw/pci-bridge/cxl_downstream: Set default link width and link speed
Without these being set the PCIE Link Capabilities register has invalid values in these two fields. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20231023160806.13206-10-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -210,6 +210,19 @@ static void cxl_dsp_exitfn(PCIDevice *d)
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pci_bridge_exitfn(d);
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}
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static void cxl_dsp_instance_post_init(Object *obj)
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{
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PCIESlot *s = PCIE_SLOT(obj);
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if (!s->speed) {
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s->speed = QEMU_PCI_EXP_LNK_2_5GT;
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}
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if (!s->width) {
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s->width = QEMU_PCI_EXP_LNK_X1;
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}
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}
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static void cxl_dsp_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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@ -230,6 +243,7 @@ static const TypeInfo cxl_dsp_info = {
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.name = TYPE_CXL_DSP,
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.instance_size = sizeof(CXLDownstreamPort),
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.parent = TYPE_PCIE_SLOT,
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.instance_post_init = cxl_dsp_instance_post_init,
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.class_init = cxl_dsp_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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