More TCG conversions for CRIS.
* Bit swap insn (bitwise not, endian swap and bit reverse). * Muls and mulu. * Extended arithmetics. * Parts of the condition code handling. * Use tcg_const_tl. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4069 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
87e92502c6
commit
3157a0a93b
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@ -153,9 +153,9 @@ int preg_sizes[] = {
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};
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#define t_gen_mov_TN_env(tn, member) \
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_t_gen_mov_TN_env((tn), offsetof(CPUState, (member)))
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_t_gen_mov_TN_env((tn), offsetof(CPUState, member))
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#define t_gen_mov_env_TN(member, tn) \
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_t_gen_mov_env_TN(offsetof(CPUState, (member)), (tn))
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_t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
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#define t_gen_mov_TN_reg(tn, regno) \
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_t_gen_mov_TN_env((tn), offsetof(CPUState, regs[regno]))
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@ -174,9 +174,9 @@ static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
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static inline void t_gen_mov_TN_preg(TCGv tn, int r)
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{
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if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
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tcg_gen_mov_tl(tn, tcg_const_i32(0));
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tcg_gen_mov_tl(tn, tcg_const_tl(0));
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else if (r == PR_VR)
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tcg_gen_mov_tl(tn, tcg_const_i32(32));
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tcg_gen_mov_tl(tn, tcg_const_tl(32));
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else
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tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUState, pregs[r]));
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}
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@ -200,7 +200,7 @@ static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
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l1 = gen_new_label();
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/* Speculative shift. */
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tcg_gen_shl_tl(d, a, b);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(d, 0);
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gen_set_label(l1);
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@ -213,7 +213,7 @@ static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
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l1 = gen_new_label();
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/* Speculative shift. */
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tcg_gen_shr_tl(d, a, b);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(d, 0);
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gen_set_label(l1);
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@ -226,14 +226,174 @@ static void t_gen_asr(TCGv d, TCGv a, TCGv b)
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l1 = gen_new_label();
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/* Speculative shift. */
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tcg_gen_sar_tl(d, a, b);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_i32(31), l1);
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tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
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/* Clear dst if shift operands were to large. */
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tcg_gen_movi_tl(d, 0);
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tcg_gen_brcond_tl(TCG_COND_LT, b, tcg_const_i32(0x80000000), l1);
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tcg_gen_brcond_tl(TCG_COND_LT, b, tcg_const_tl(0x80000000), l1);
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tcg_gen_movi_tl(d, 0xffffffff);
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gen_set_label(l1);
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}
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/* 64-bit signed mul, lower result in d and upper in d2. */
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static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
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{
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TCGv t0, t1;
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t0 = tcg_temp_new(TCG_TYPE_I64);
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t1 = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_ext32s_i64(t0, a);
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tcg_gen_ext32s_i64(t1, b);
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tcg_gen_mul_i64(t0, t0, t1);
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tcg_gen_trunc_i64_i32(d, t0);
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_trunc_i64_i32(d2, t0);
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}
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/* 64-bit unsigned muls, lower result in d and upper in d2. */
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static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
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{
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TCGv t0, t1;
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t0 = tcg_temp_new(TCG_TYPE_I64);
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t1 = tcg_temp_new(TCG_TYPE_I64);
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tcg_gen_extu_i32_i64(t0, a);
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tcg_gen_extu_i32_i64(t1, b);
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tcg_gen_mul_i64(t0, t0, t1);
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tcg_gen_trunc_i64_i32(d, t0);
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tcg_gen_shri_i64(t0, t0, 32);
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tcg_gen_trunc_i64_i32(d2, t0);
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}
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/* Extended arithmetics on CRIS. */
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static inline void t_gen_add_flag(TCGv d, int flag)
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{
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TCGv c;
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c = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mov_TN_preg(c, PR_CCS);
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/* Propagate carry into d. */
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tcg_gen_andi_tl(c, c, 1 << flag);
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if (flag)
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tcg_gen_shri_tl(c, c, flag);
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tcg_gen_add_tl(d, d, c);
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}
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static inline void t_gen_addx_carry(TCGv d)
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{
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TCGv x, c;
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x = tcg_temp_new(TCG_TYPE_TL);
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c = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mov_TN_preg(x, PR_CCS);
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tcg_gen_mov_tl(c, x);
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/* Propagate carry into d if X is set. Branch free. */
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tcg_gen_andi_tl(c, c, C_FLAG);
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tcg_gen_andi_tl(x, x, X_FLAG);
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tcg_gen_shri_tl(x, x, 4);
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tcg_gen_and_tl(x, x, c);
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tcg_gen_add_tl(d, d, x);
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}
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static inline void t_gen_subx_carry(TCGv d)
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{
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TCGv x, c;
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x = tcg_temp_new(TCG_TYPE_TL);
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c = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mov_TN_preg(x, PR_CCS);
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tcg_gen_mov_tl(c, x);
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/* Propagate carry into d if X is set. Branch free. */
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tcg_gen_andi_tl(c, c, C_FLAG);
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tcg_gen_andi_tl(x, x, X_FLAG);
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tcg_gen_shri_tl(x, x, 4);
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tcg_gen_and_tl(x, x, c);
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tcg_gen_sub_tl(d, d, x);
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}
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/* Swap the two bytes within each half word of the s operand.
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T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
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static inline void t_gen_swapb(TCGv d, TCGv s)
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{
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TCGv t, org_s;
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t = tcg_temp_new(TCG_TYPE_TL);
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org_s = tcg_temp_new(TCG_TYPE_TL);
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/* d and s may refer to the same object. */
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tcg_gen_mov_tl(org_s, s);
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tcg_gen_shli_tl(t, org_s, 8);
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tcg_gen_andi_tl(d, t, 0xff00ff00);
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tcg_gen_shri_tl(t, org_s, 8);
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tcg_gen_andi_tl(t, t, 0x00ff00ff);
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tcg_gen_or_tl(d, d, t);
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}
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/* Swap the halfwords of the s operand. */
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static inline void t_gen_swapw(TCGv d, TCGv s)
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{
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TCGv t;
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/* d and s refer the same object. */
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t = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_mov_tl(t, s);
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tcg_gen_shli_tl(d, t, 16);
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tcg_gen_shri_tl(t, t, 16);
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tcg_gen_or_tl(d, d, t);
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}
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/* Reverse the within each byte.
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T0 = (((T0 << 7) & 0x80808080) |
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((T0 << 5) & 0x40404040) |
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((T0 << 3) & 0x20202020) |
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((T0 << 1) & 0x10101010) |
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((T0 >> 1) & 0x08080808) |
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((T0 >> 3) & 0x04040404) |
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((T0 >> 5) & 0x02020202) |
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((T0 >> 7) & 0x01010101));
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*/
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static inline void t_gen_swapr(TCGv d, TCGv s)
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{
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struct {
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int shift; /* LSL when positive, LSR when negative. */
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uint32_t mask;
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} bitrev [] = {
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{7, 0x80808080},
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{5, 0x40404040},
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{3, 0x20202020},
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{1, 0x10101010},
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{-1, 0x08080808},
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{-3, 0x04040404},
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{-5, 0x02020202},
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{-7, 0x01010101}
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};
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int i;
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TCGv t, org_s;
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/* d and s refer the same object. */
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t = tcg_temp_new(TCG_TYPE_TL);
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org_s = tcg_temp_new(TCG_TYPE_TL);
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tcg_gen_mov_tl(org_s, s);
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tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
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tcg_gen_andi_tl(d, t, bitrev[0].mask);
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for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
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if (bitrev[i].shift >= 0) {
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tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
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} else {
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tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
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}
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tcg_gen_andi_tl(t, t, bitrev[i].mask);
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tcg_gen_or_tl(d, d, t);
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}
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}
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static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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{
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TranslationBlock *tb;
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@ -241,10 +401,10 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
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if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
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tcg_gen_goto_tb(n);
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tcg_gen_movi_tl(cpu_T[0], dest);
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gen_op_movl_pc_T0();
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t_gen_mov_env_TN(pc, cpu_T[0]);
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tcg_gen_exit_tb((long)tb + n);
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} else {
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gen_op_movl_pc_T0();
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t_gen_mov_env_TN(pc, cpu_T[0]);
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tcg_gen_exit_tb(0);
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}
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}
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@ -264,13 +424,9 @@ static int sign_extend(unsigned int val, unsigned int width)
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static inline void cris_clear_x_flag(DisasContext *dc)
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{
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TCGv ccs;
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ccs = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mov_TN_preg(ccs, PR_CCS);
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tcg_gen_andi_i32(ccs, ccs, ~X_FLAG);
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t_gen_mov_preg_TN(PR_CCS, ccs);
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t_gen_mov_TN_preg(cpu_T[0], PR_CCS);
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tcg_gen_andi_i32(cpu_T[0], cpu_T[0], ~X_FLAG);
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t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
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dc->flagx_live = 1;
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dc->flags_x = 0;
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}
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@ -339,7 +495,7 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
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if (mask == 0)
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dc->update_cc = 0;
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else {
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gen_op_update_cc_mask(mask);
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t_gen_mov_env_TN(cc_mask, tcg_const_tl(mask));
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dc->flags_live = 0;
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}
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}
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@ -347,13 +503,13 @@ static void cris_cc_mask(DisasContext *dc, unsigned int mask)
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static void cris_update_cc_op(DisasContext *dc, int op)
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{
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dc->cc_op = op;
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gen_op_update_cc_op(op);
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dc->flags_live = 0;
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t_gen_mov_env_TN(cc_op, tcg_const_tl(op));
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}
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static void cris_update_cc_size(DisasContext *dc, int size)
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{
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dc->cc_size = size;
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gen_op_update_cc_size_im(size);
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t_gen_mov_env_TN(cc_size, tcg_const_tl(size));
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}
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/* op is the operation.
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@ -364,10 +520,15 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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{
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int writeback = 1;
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if (dc->update_cc) {
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cris_update_cc_op(dc, op);
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cris_update_cc_size(dc, size);
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gen_op_update_cc_x(dc->flagx_live, dc->flags_x);
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gen_op_update_cc_dest_T0();
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t_gen_mov_env_TN(cc_dest, cpu_T[0]);
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/* FIXME: This shouldn't be needed. But we don't pass the
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tests without it. Investigate. */
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t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
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t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
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}
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/* Emit the ALU insns. */
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@ -376,25 +537,25 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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case CC_OP_ADD:
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tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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/* Extended arithmetics. */
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gen_op_addxl_T0_C();
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t_gen_addx_carry(cpu_T[0]);
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break;
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case CC_OP_ADDC:
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tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_addl_T0_C();
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t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
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break;
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case CC_OP_MCP:
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tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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gen_op_addl_T0_R();
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t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
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break;
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case CC_OP_SUB:
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tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
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tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
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tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
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tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
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/* CRIS flag evaluation needs ~src. */
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tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
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gen_op_not_T1_T1();
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tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
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/* Extended arithmetics. */
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gen_op_subxl_T0_C();
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t_gen_subx_carry(cpu_T[0]);
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break;
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case CC_OP_MOVE:
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tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
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@ -418,11 +579,11 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
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break;
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case CC_OP_NEG:
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/* TCG-FIXME: this is not optimal. Many archs have
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fast neg insns. */
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tcg_gen_sub_tl(cpu_T[0], tcg_const_i32(0), cpu_T[1]);
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/* Hopefully the TCG backend recognizes this pattern
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and makes a real neg out of it. */
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tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
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/* Extended arithmetics. */
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gen_op_subxl_T0_C();
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t_gen_subx_carry(cpu_T[0]);
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break;
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case CC_OP_LZ:
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gen_op_lz_T0_T1();
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@ -432,27 +593,44 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
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writeback = 0;
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break;
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case CC_OP_MULS:
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gen_op_muls_T0_T1();
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break;
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{
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TCGv mof;
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mof = tcg_temp_new(TCG_TYPE_TL);
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t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
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t_gen_mov_preg_TN(PR_MOF, mof);
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}
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break;
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case CC_OP_MULU:
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gen_op_mulu_T0_T1();
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break;
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{
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TCGv mof;
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mof = tcg_temp_new(TCG_TYPE_TL);
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t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
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t_gen_mov_preg_TN(PR_MOF, mof);
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}
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break;
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case CC_OP_DSTEP:
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gen_op_dstep_T0_T1();
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break;
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case CC_OP_BOUND:
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gen_op_bound_T0_T1();
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break;
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{
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int l1;
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l1 = gen_new_label();
|
||||
tcg_gen_brcond_tl(TCG_COND_LEU,
|
||||
cpu_T[0], cpu_T[1], l1);
|
||||
tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
|
||||
gen_set_label(l1);
|
||||
}
|
||||
break;
|
||||
case CC_OP_CMP:
|
||||
tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
|
||||
tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
|
||||
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
||||
/* CRIS flag evaluation needs ~src. */
|
||||
tcg_gen_sub_tl(cpu_T[1], tcg_const_i32(0), cpu_T[1]);
|
||||
tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
|
||||
/* CRIS flag evaluation needs ~src. */
|
||||
gen_op_not_T1_T1();
|
||||
tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
|
||||
|
||||
/* Extended arithmetics. */
|
||||
gen_op_subxl_T0_C();
|
||||
t_gen_subx_carry(cpu_T[0]);
|
||||
writeback = 0;
|
||||
break;
|
||||
default:
|
||||
|
|
@ -462,7 +640,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
|
|||
}
|
||||
|
||||
if (dc->update_cc)
|
||||
gen_op_update_cc_src_T1();
|
||||
t_gen_mov_env_TN(cc_src, cpu_T[1]);
|
||||
|
||||
if (size == 1)
|
||||
tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
|
||||
|
|
@ -486,7 +664,7 @@ static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
|
|||
}
|
||||
}
|
||||
if (dc->update_cc)
|
||||
gen_op_update_cc_result_T0();
|
||||
t_gen_mov_env_TN(cc_result, cpu_T[0]);
|
||||
|
||||
{
|
||||
/* TODO: Optimize this. */
|
||||
|
|
@ -617,8 +795,8 @@ static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
|
|||
gen_tst_cc (dc, cond);
|
||||
gen_op_evaluate_bcc ();
|
||||
}
|
||||
gen_op_movl_T0_im (dc->delayed_pc);
|
||||
gen_op_movl_btarget_T0 ();
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->delayed_pc);
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
}
|
||||
|
||||
/* Dynamic jumps, when the dest is in a live reg for example. */
|
||||
|
|
@ -726,7 +904,7 @@ static void do_postinc (DisasContext *dc, int size)
|
|||
if (!dc->postinc)
|
||||
return;
|
||||
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
|
||||
gen_op_addl_T0_im(size);
|
||||
tcg_gen_addi_tl(cpu_T[0], cpu_T[0], size);
|
||||
t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
|
||||
}
|
||||
|
||||
|
|
@ -874,7 +1052,7 @@ static unsigned int dec_moveq(DisasContext *dc)
|
|||
imm = sign_extend(dc->op1, 5);
|
||||
DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
|
||||
|
||||
t_gen_mov_reg_TN(dc->op2, tcg_const_i32(imm));
|
||||
t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
|
||||
if (!dc->flagx_live || dc->flags_x)
|
||||
cris_clear_x_flag(dc);
|
||||
return 2;
|
||||
|
|
@ -940,7 +1118,7 @@ static unsigned int dec_btstq(DisasContext *dc)
|
|||
crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
|
||||
|
||||
cris_update_cc_op(dc, CC_OP_FLAGS);
|
||||
gen_op_movl_flags_T0();
|
||||
t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
|
||||
dc->flags_live = 1;
|
||||
return 2;
|
||||
}
|
||||
|
|
@ -1000,10 +1178,10 @@ static unsigned int dec_scc_r(DisasContext *dc)
|
|||
if (cond != CC_A)
|
||||
{
|
||||
gen_tst_cc (dc, cond);
|
||||
gen_op_movl_T1_T0();
|
||||
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
|
||||
}
|
||||
else
|
||||
gen_op_movl_T1_im(1);
|
||||
tcg_gen_movi_tl(cpu_T[1], 1);
|
||||
|
||||
cris_cc_mask(dc, 0);
|
||||
crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
|
||||
|
|
@ -1147,11 +1325,18 @@ static unsigned int dec_cmp_r(DisasContext *dc)
|
|||
|
||||
static unsigned int dec_abs_r(DisasContext *dc)
|
||||
{
|
||||
int l1;
|
||||
|
||||
DIS(fprintf (logfile, "abs $r%u, $r%u\n",
|
||||
dc->op1, dc->op2));
|
||||
cris_cc_mask(dc, CC_MASK_NZ);
|
||||
dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
|
||||
gen_op_absl_T1_T1();
|
||||
|
||||
/* TODO: consider a branch free approach. */
|
||||
l1 = gen_new_label();
|
||||
tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
|
||||
tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
|
||||
gen_set_label(l1);
|
||||
crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
|
||||
return 2;
|
||||
}
|
||||
|
|
@ -1215,14 +1400,14 @@ static unsigned int dec_swap_r(DisasContext *dc)
|
|||
cris_cc_mask(dc, CC_MASK_NZ);
|
||||
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
|
||||
if (dc->op2 & 8)
|
||||
gen_op_not_T0_T0();
|
||||
tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
|
||||
if (dc->op2 & 4)
|
||||
gen_op_swapw_T0_T0();
|
||||
t_gen_swapw(cpu_T[0], cpu_T[0]);
|
||||
if (dc->op2 & 2)
|
||||
gen_op_swapb_T0_T0();
|
||||
t_gen_swapb(cpu_T[0], cpu_T[0]);
|
||||
if (dc->op2 & 1)
|
||||
gen_op_swapr_T0_T0();
|
||||
gen_op_movl_T1_T0();
|
||||
t_gen_swapr(cpu_T[0], cpu_T[0]);
|
||||
tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
|
||||
crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
|
||||
return 2;
|
||||
}
|
||||
|
|
@ -1244,7 +1429,7 @@ static unsigned int dec_addi_r(DisasContext *dc)
|
|||
memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
|
||||
cris_cc_mask(dc, 0);
|
||||
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
|
||||
t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_i32(dc->zzsize));
|
||||
t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
|
||||
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
||||
t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
|
||||
return 2;
|
||||
|
|
@ -1256,7 +1441,7 @@ static unsigned int dec_addi_acr(DisasContext *dc)
|
|||
memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
|
||||
cris_cc_mask(dc, 0);
|
||||
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
|
||||
t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_i32(dc->zzsize));
|
||||
t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
|
||||
|
||||
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
|
||||
t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
|
||||
|
|
@ -1283,7 +1468,7 @@ static unsigned int dec_btst_r(DisasContext *dc)
|
|||
crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
|
||||
|
||||
cris_update_cc_op(dc, CC_OP_FLAGS);
|
||||
gen_op_movl_flags_T0();
|
||||
t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
|
||||
dc->flags_live = 1;
|
||||
return 2;
|
||||
}
|
||||
|
|
@ -1910,7 +2095,7 @@ static unsigned int dec_lapc_im(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
imm = ldl_code(dc->pc + 2);
|
||||
DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
|
||||
t_gen_mov_reg_TN(rd, tcg_const_i32(dc->pc + imm));
|
||||
t_gen_mov_reg_TN(rd, tcg_const_tl(dc->pc + imm));
|
||||
return 6;
|
||||
}
|
||||
|
||||
|
|
@ -1921,7 +2106,7 @@ static unsigned int dec_jump_p(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
/* Store the return address in Pd. */
|
||||
t_gen_mov_TN_preg(cpu_T[0], dc->op2);
|
||||
gen_op_movl_btarget_T0();
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
return 2;
|
||||
}
|
||||
|
|
@ -1933,7 +2118,7 @@ static unsigned int dec_jas_r(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
|
||||
gen_op_movl_btarget_T0();
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
|
||||
t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
|
|
@ -1950,7 +2135,7 @@ static unsigned int dec_jas_im(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
tcg_gen_movi_tl(cpu_T[0], imm);
|
||||
gen_op_movl_btarget_T0();
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
|
||||
t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
|
|
@ -1967,7 +2152,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
tcg_gen_movi_tl(cpu_T[0], imm);
|
||||
gen_op_movl_btarget_T0();
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
|
||||
t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
|
|
@ -1980,7 +2165,7 @@ static unsigned int dec_jasc_r(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
t_gen_mov_TN_reg(cpu_T[0], dc->op1);
|
||||
gen_op_movl_btarget_T0();
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
|
||||
t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
|
|
@ -2016,7 +2201,7 @@ static unsigned int dec_bas_im(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
|
||||
gen_op_movl_btarget_T0();
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
|
||||
t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
|
|
@ -2032,7 +2217,7 @@ static unsigned int dec_basc_im(DisasContext *dc)
|
|||
cris_cc_mask(dc, 0);
|
||||
/* Stor the return address in Pd. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
|
||||
gen_op_movl_btarget_T0();
|
||||
t_gen_mov_env_TN(btarget, cpu_T[0]);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
|
||||
t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
|
||||
cris_prepare_dyn_jmp(dc);
|
||||
|
|
@ -2062,7 +2247,7 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
|
|||
case 6:
|
||||
/* break. */
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
||||
gen_op_movl_pc_T0();
|
||||
t_gen_mov_env_TN(pc, cpu_T[0]);
|
||||
/* Breaks start at 16 in the exception vector. */
|
||||
gen_op_break_im(dc->op1 + 16);
|
||||
dc->is_jmp = DISAS_SWI;
|
||||
|
|
@ -2247,7 +2432,7 @@ static void check_breakpoint(CPUState *env, DisasContext *dc)
|
|||
if (env->breakpoints[j] == dc->pc) {
|
||||
cris_evaluate_flags (dc);
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
||||
gen_op_movl_pc_T0();
|
||||
t_gen_mov_env_TN(pc, cpu_T[0]);
|
||||
gen_op_debug();
|
||||
dc->is_jmp = DISAS_UPDATE;
|
||||
}
|
||||
|
|
@ -2279,6 +2464,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
dc->singlestep_enabled = env->singlestep_enabled;
|
||||
dc->flagx_live = 0;
|
||||
dc->flags_x = 0;
|
||||
|
||||
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
|
||||
lj = -1;
|
||||
do
|
||||
|
|
@ -2333,8 +2519,8 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
|
|||
&& dc->pc < next_page_start);
|
||||
|
||||
if (!dc->is_jmp) {
|
||||
gen_op_movl_T0_im((long)dc->pc);
|
||||
gen_op_movl_pc_T0();
|
||||
tcg_gen_movi_tl(cpu_T[0], dc->pc);
|
||||
t_gen_mov_env_TN(pc, cpu_T[0]);
|
||||
}
|
||||
|
||||
cris_evaluate_flags (dc);
|
||||
|
|
|
|||
Loading…
Reference in New Issue