m48t59: let init functions return a Nvram object
Remove left-overs from header file. Move some functions only used by PReP to hw/ppc/prep.c Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> CC: Andreas Färber <afaerber@suse.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Hervé Poussineau
Mark Cave-Ayland
parent
4374532888
commit
3168824682
161
hw/ppc/ppc.c
161
hw/ppc/ppc.c
@ -1318,167 +1318,6 @@ void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
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}
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}
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/*****************************************************************************/
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/* NVRAM helpers */
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static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
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{
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return (*nvram->read_fn)(nvram->opaque, addr);
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}
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static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
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{
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(*nvram->write_fn)(nvram->opaque, addr, val);
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}
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static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value)
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{
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nvram_write(nvram, addr, value);
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}
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static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr)
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{
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return nvram_read(nvram, addr);
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}
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static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value)
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{
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nvram_write(nvram, addr, value >> 8);
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nvram_write(nvram, addr + 1, value & 0xFF);
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}
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static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr)
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{
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uint16_t tmp;
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tmp = nvram_read(nvram, addr) << 8;
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tmp |= nvram_read(nvram, addr + 1);
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return tmp;
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}
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static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value)
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{
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nvram_write(nvram, addr, value >> 24);
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nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
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nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
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nvram_write(nvram, addr + 3, value & 0xFF);
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}
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uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
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{
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uint32_t tmp;
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tmp = nvram_read(nvram, addr) << 24;
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tmp |= nvram_read(nvram, addr + 1) << 16;
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tmp |= nvram_read(nvram, addr + 2) << 8;
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tmp |= nvram_read(nvram, addr + 3);
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return tmp;
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}
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static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str,
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uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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nvram_write(nvram, addr + i, str[i]);
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}
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nvram_write(nvram, addr + i, str[i]);
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nvram_write(nvram, addr + max - 1, '\0');
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}
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int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
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{
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int i;
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memset(dst, 0, max);
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for (i = 0; i < max; i++) {
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dst[i] = NVRAM_get_byte(nvram, addr + i);
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if (dst[i] == '\0')
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break;
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}
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return i;
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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#define CMDLINE_ADDR 0x017ff000
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int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
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const char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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if (cmdline) {
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/* XXX: put the cmdline in NVRAM too ? */
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pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
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NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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} else {
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NVRAM_set_lword(nvram, 0x40, 0);
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NVRAM_set_lword(nvram, 0x44, 0);
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}
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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NVRAM_set_word(nvram, 0x54, width);
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NVRAM_set_word(nvram, 0x56, height);
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NVRAM_set_word(nvram, 0x58, depth);
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crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
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NVRAM_set_word(nvram, 0xFC, crc);
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return 0;
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}
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/* CPU device-tree ID helpers */
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int ppc_get_vcpu_dt_id(PowerPCCPU *cpu)
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{
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161
hw/ppc/prep.c
161
hw/ppc/prep.c
@ -181,7 +181,7 @@ static const MemoryRegionOps PPC_XCSR_ops = {
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/* Fake super-io ports for PREP platform (Intel 82378ZB) */
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typedef struct sysctrl_t {
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qemu_irq reset_irq;
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M48t59State *nvram;
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Nvram *nvram;
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uint8_t state;
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uint8_t syscontrol;
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int contiguous_map;
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@ -235,13 +235,17 @@ static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
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break;
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case 0x0810:
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/* Password protect 1 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 1);
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 1);
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}
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break;
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case 0x0812:
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/* Password protect 2 register */
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if (sysctrl->nvram != NULL)
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m48t59_toggle_lock(sysctrl->nvram, 2);
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if (sysctrl->nvram != NULL) {
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->toggle_lock)(sysctrl->nvram, 2);
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}
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break;
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case 0x0814:
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/* L2 invalidate register */
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@ -360,6 +364,144 @@ static const MemoryRegionPortio prep_portio_list[] = {
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static PortioList prep_port_list;
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/*****************************************************************************/
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/* NVRAM helpers */
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static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
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{
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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return (k->read)(nvram, addr);
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}
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static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
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{
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NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
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(k->write)(nvram, addr, val);
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}
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static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
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{
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nvram_write(nvram, addr, value);
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}
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static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
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{
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return nvram_read(nvram, addr);
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}
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static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
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{
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nvram_write(nvram, addr, value >> 8);
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nvram_write(nvram, addr + 1, value & 0xFF);
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}
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static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
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{
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uint16_t tmp;
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tmp = nvram_read(nvram, addr) << 8;
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tmp |= nvram_read(nvram, addr + 1);
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return tmp;
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}
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static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
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{
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nvram_write(nvram, addr, value >> 24);
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nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
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nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
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nvram_write(nvram, addr + 3, value & 0xFF);
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}
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static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
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uint32_t max)
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{
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int i;
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for (i = 0; i < max && str[i] != '\0'; i++) {
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nvram_write(nvram, addr + i, str[i]);
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}
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nvram_write(nvram, addr + i, str[i]);
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nvram_write(nvram, addr + max - 1, '\0');
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}
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static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
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{
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uint16_t tmp;
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uint16_t pd, pd1, pd2;
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tmp = prev >> 8;
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pd = prev ^ value;
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pd1 = pd & 0x000F;
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pd2 = ((pd >> 4) & 0x000F) ^ pd1;
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tmp ^= (pd1 << 3) | (pd1 << 8);
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tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
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return tmp;
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}
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static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
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{
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uint32_t i;
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uint16_t crc = 0xFFFF;
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int odd;
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odd = count & 1;
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count &= ~1;
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for (i = 0; i != count; i++) {
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crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
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}
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if (odd) {
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crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
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}
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return crc;
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}
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#define CMDLINE_ADDR 0x017ff000
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static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
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const char *arch,
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uint32_t RAM_size, int boot_device,
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uint32_t kernel_image, uint32_t kernel_size,
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const char *cmdline,
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uint32_t initrd_image, uint32_t initrd_size,
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uint32_t NVRAM_image,
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int width, int height, int depth)
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{
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uint16_t crc;
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/* Set parameters for Open Hack'Ware BIOS */
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NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
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NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
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NVRAM_set_word(nvram, 0x14, NVRAM_size);
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NVRAM_set_string(nvram, 0x20, arch, 16);
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NVRAM_set_lword(nvram, 0x30, RAM_size);
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NVRAM_set_byte(nvram, 0x34, boot_device);
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NVRAM_set_lword(nvram, 0x38, kernel_image);
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NVRAM_set_lword(nvram, 0x3C, kernel_size);
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if (cmdline) {
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/* XXX: put the cmdline in NVRAM too ? */
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pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
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cmdline);
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NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
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NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
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} else {
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NVRAM_set_lword(nvram, 0x40, 0);
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NVRAM_set_lword(nvram, 0x44, 0);
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}
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NVRAM_set_lword(nvram, 0x48, initrd_image);
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NVRAM_set_lword(nvram, 0x4C, initrd_size);
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NVRAM_set_lword(nvram, 0x50, NVRAM_image);
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NVRAM_set_word(nvram, 0x54, width);
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NVRAM_set_word(nvram, 0x56, height);
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NVRAM_set_word(nvram, 0x58, depth);
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crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
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NVRAM_set_word(nvram, 0xFC, crc);
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return 0;
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}
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/* PowerPC PREP hardware initialisation */
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static void ppc_prep_init(MachineState *machine)
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{
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@ -372,8 +514,7 @@ static void ppc_prep_init(MachineState *machine)
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MemoryRegion *sysmem = get_system_memory();
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PowerPCCPU *cpu = NULL;
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CPUPPCState *env = NULL;
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nvram_t nvram;
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M48t59State *m48t59;
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Nvram *m48t59;
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#if 0
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MemoryRegion *xcsr = g_new(MemoryRegion, 1);
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#endif
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@ -549,10 +690,8 @@ static void ppc_prep_init(MachineState *machine)
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sysctrl->nvram = m48t59;
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/* Initialise NVRAM */
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nvram.opaque = m48t59;
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nvram.read_fn = &m48t59_read;
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nvram.write_fn = &m48t59_write;
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PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
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PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
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ppc_boot_device,
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kernel_base, kernel_size,
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kernel_cmdline,
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initrd_base, initrd_size,
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@ -127,7 +127,7 @@ static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
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static void nvram_init(Nvram *nvram, uint8_t *macaddr,
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const char *cmdline, const char *boot_devices,
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ram_addr_t RAM_size, uint32_t kernel_size,
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int width, int height, int depth,
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@ -137,6 +137,7 @@ static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
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uint32_t start, end;
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uint8_t image[0x1ff0];
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struct OpenBIOS_nvpart_v1 *part_header;
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NvramClass *k = NVRAM_GET_CLASS(nvram);
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memset(image, '\0', sizeof(image));
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@ -170,8 +171,9 @@ static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
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Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
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nvram_machine_id);
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for (i = 0; i < sizeof(image); i++)
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m48t59_write(nvram, i, image[i]);
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for (i = 0; i < sizeof(image); i++) {
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(k->write)(nvram, i, image[i]);
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}
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}
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static DeviceState *slavio_intctl;
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@ -130,7 +130,7 @@ static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
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static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
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const char *arch, ram_addr_t RAM_size,
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const char *boot_devices,
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uint32_t kernel_image, uint32_t kernel_size,
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@ -144,6 +144,7 @@ static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
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uint32_t start, end;
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uint8_t image[0x1ff0];
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||||
struct OpenBIOS_nvpart_v1 *part_header;
|
||||
NvramClass *k = NVRAM_GET_CLASS(nvram);
|
||||
|
||||
memset(image, '\0', sizeof(image));
|
||||
|
||||
@ -176,8 +177,9 @@ static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
|
||||
|
||||
Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
|
||||
|
||||
for (i = 0; i < sizeof(image); i++)
|
||||
m48t59_write(nvram, i, image[i]);
|
||||
for (i = 0; i < sizeof(image); i++) {
|
||||
(k->write)(nvram, i, image[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -818,7 +820,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
|
||||
const struct hwdef *hwdef)
|
||||
{
|
||||
SPARCCPU *cpu;
|
||||
M48t59State *nvram;
|
||||
Nvram *nvram;
|
||||
unsigned int i;
|
||||
uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
|
||||
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
|
||||
|
||||
@ -74,7 +74,7 @@ typedef struct M48txxInfo {
|
||||
* http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
|
||||
*/
|
||||
|
||||
struct M48t59State {
|
||||
typedef struct M48t59State {
|
||||
/* Hardware parameters */
|
||||
qemu_irq IRQ;
|
||||
MemoryRegion iomem;
|
||||
@ -93,7 +93,7 @@ struct M48t59State {
|
||||
/* NVRAM storage */
|
||||
uint16_t addr;
|
||||
uint8_t lock;
|
||||
};
|
||||
} M48t59State;
|
||||
|
||||
typedef struct M48txxISAState {
|
||||
ISADevice parent_obj;
|
||||
@ -240,9 +240,8 @@ static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
|
||||
}
|
||||
|
||||
/* Direct access to NVRAM */
|
||||
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
|
||||
static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
|
||||
{
|
||||
M48t59State *NVRAM = opaque;
|
||||
struct tm tm;
|
||||
int tmp;
|
||||
|
||||
@ -410,9 +409,8 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t m48t59_read (void *opaque, uint32_t addr)
|
||||
static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
|
||||
{
|
||||
M48t59State *NVRAM = opaque;
|
||||
struct tm tm;
|
||||
uint32_t retval = 0xFF;
|
||||
|
||||
@ -519,10 +517,8 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
|
||||
return retval;
|
||||
}
|
||||
|
||||
void m48t59_toggle_lock (void *opaque, int lock)
|
||||
static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
|
||||
{
|
||||
M48t59State *NVRAM = opaque;
|
||||
|
||||
NVRAM->lock ^= 1 << lock;
|
||||
}
|
||||
|
||||
@ -683,13 +679,11 @@ static const MemoryRegionOps m48t59_io_ops = {
|
||||
};
|
||||
|
||||
/* Initialisation routine */
|
||||
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int model)
|
||||
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int model)
|
||||
{
|
||||
DeviceState *dev;
|
||||
SysBusDevice *s;
|
||||
M48txxSysBusState *d;
|
||||
M48t59State *state;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
|
||||
@ -702,8 +696,6 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
|
||||
qdev_init_nofail(dev);
|
||||
s = SYS_BUS_DEVICE(dev);
|
||||
d = M48TXX_SYS_BUS(s);
|
||||
state = &d->state;
|
||||
sysbus_connect_irq(s, 0, IRQ);
|
||||
if (io_base != 0) {
|
||||
memory_region_add_subregion(get_system_io(), io_base,
|
||||
@ -713,15 +705,15 @@ M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
sysbus_mmio_map(s, 0, mem_base);
|
||||
}
|
||||
|
||||
return state;
|
||||
return NVRAM(s);
|
||||
}
|
||||
|
||||
assert(false);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int model)
|
||||
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int model)
|
||||
{
|
||||
DeviceState *dev;
|
||||
int i;
|
||||
@ -736,7 +728,7 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
|
||||
qdev_prop_set_uint32(dev, "iobase", io_base);
|
||||
qdev_init_nofail(dev);
|
||||
return &M48TXX_ISA(dev)->state;
|
||||
return NVRAM(dev);
|
||||
}
|
||||
|
||||
assert(false);
|
||||
|
||||
@ -4,39 +4,6 @@
|
||||
#include "qemu-common.h"
|
||||
#include "qom/object.h"
|
||||
|
||||
/* NVRAM helpers */
|
||||
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
|
||||
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
|
||||
typedef struct nvram_t {
|
||||
void *opaque;
|
||||
nvram_read_t read_fn;
|
||||
nvram_write_t write_fn;
|
||||
} nvram_t;
|
||||
|
||||
uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr);
|
||||
int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max);
|
||||
|
||||
int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
||||
const char *arch,
|
||||
uint32_t RAM_size, int boot_device,
|
||||
uint32_t kernel_image, uint32_t kernel_size,
|
||||
const char *cmdline,
|
||||
uint32_t initrd_image, uint32_t initrd_size,
|
||||
uint32_t NVRAM_image,
|
||||
int width, int height, int depth);
|
||||
|
||||
#define TYPE_SYSBUS_M48T59 "m48t59"
|
||||
|
||||
typedef struct M48t59State M48t59State;
|
||||
|
||||
void m48t59_write (void *private, uint32_t addr, uint32_t val);
|
||||
uint32_t m48t59_read (void *private, uint32_t addr);
|
||||
void m48t59_toggle_lock (void *private, int lock);
|
||||
M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int type);
|
||||
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int type);
|
||||
|
||||
#define TYPE_NVRAM "nvram"
|
||||
|
||||
#define NVRAM_CLASS(klass) \
|
||||
@ -58,4 +25,9 @@ typedef struct NvramClass {
|
||||
void (*toggle_lock)(Nvram *obj, int lock);
|
||||
} NvramClass;
|
||||
|
||||
Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
|
||||
int type);
|
||||
Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
|
||||
uint32_t io_base, uint16_t size, int type);
|
||||
|
||||
#endif /* !NVRAM_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user