escc: update the R_SPEC register SPEC_ALLSENT bit when writing to W_TXCTRL1
The ESCC datasheet states that SPEC_ALLSENT is always set in sync mode and set in async mode once all characters have cleared the transmitter. Since writes to SERIAL_DATA use a synchronous chardev API, the guest can never see the state when transmission is in progress so it is possible to set SPEC_ALLSENT in the R_SPEC register unconditionally. This fixes a hang when using the Sun PROM as it attempts to enumerate the onboard serial devices, and a similar hang in OpenBSD SPARC32 where in both cases the boot process will not proceed until SPEC_ALLSENT has been set after writing to W_TXCTRL1. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20211118181835.18497-3-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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@ -586,6 +586,20 @@ static void escc_mem_write(void *opaque, hwaddr addr,
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s->wregs[s->reg] = val;
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s->wregs[s->reg] = val;
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break;
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break;
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case W_TXCTRL1:
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case W_TXCTRL1:
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s->wregs[s->reg] = val;
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/*
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* The ESCC datasheet states that SPEC_ALLSENT is always set in
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* sync mode, and set in async mode when all characters have
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* cleared the transmitter. Since writes to SERIAL_DATA use the
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* blocking qemu_chr_fe_write_all() function to write each
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* character, the guest can never see the state when async data
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* is in the process of being transmitted so we can set this bit
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* unconditionally regardless of the state of the W_TXCTRL1 mode
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* bits.
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*/
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s->rregs[R_SPEC] |= SPEC_ALLSENT;
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escc_update_parameters(s);
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break;
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case W_TXCTRL2:
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case W_TXCTRL2:
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s->wregs[s->reg] = val;
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s->wregs[s->reg] = val;
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escc_update_parameters(s);
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escc_update_parameters(s);
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