target: e2k: Move ct cond to cpu env.
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17d175a2d8
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@ -237,6 +237,7 @@ typedef struct {
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/* control registers */
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target_ulong ctprs[4]; // Control Transfer Preparation Register (CTPR)
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target_ulong ct_cond;
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/* special registers */
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target_ulong ip; /* instruction address */
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@ -323,7 +323,7 @@ static inline void do_branch(DisasContext *ctx)
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if (ctx->ct.has_cond) {
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TCGLabel *l = gen_new_label();
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tcg_gen_brcondi_tl(TCG_COND_NE, ctx->ct.cond, 0, l);
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tcg_gen_brcondi_tl(TCG_COND_NE, e2k_cs.ct_cond, 0, l);
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tcg_gen_movi_tl(e2k_cs.pc, ctx->npc);
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tcg_gen_exit_tb(NULL, 0);
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@ -337,7 +337,7 @@ static inline void do_branch(DisasContext *ctx)
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case CT_JUMP:
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ctx->base.is_jmp = DISAS_NORETURN;
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gen_save_cpu_state(ctx);
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gen_helper_jump(e2k_cs.pc, cpu_env, ctx->ct.cond, ctx->ct.u.ctpr);
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gen_helper_jump(e2k_cs.pc, cpu_env, e2k_cs.ct_cond, ctx->ct.u.ctpr);
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tcg_gen_lookup_and_goto_ptr();
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break;
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case CT_CALL:
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@ -345,7 +345,7 @@ static inline void do_branch(DisasContext *ctx)
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TCGv_i32 wbs = tcg_const_i32(ctx->ct.wbs);
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ctx->base.is_jmp = DISAS_NORETURN;
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gen_save_cpu_state(ctx);
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gen_helper_call(e2k_cs.pc, cpu_env, ctx->ct.cond, ctx->ct.u.ctpr, wbs);
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gen_helper_call(e2k_cs.pc, cpu_env, e2k_cs.ct_cond, ctx->ct.u.ctpr, wbs);
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tcg_temp_free_i32(wbs);
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tcg_gen_lookup_and_goto_ptr();
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break;
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@ -388,7 +388,7 @@ static void e2k_tr_tb_start(DisasContextBase *db, CPUState *cs)
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{
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DisasContext *ctx = container_of(db, DisasContext, base);
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ctx->ct.cond = tcg_const_tl(1);
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tcg_gen_movi_tl(e2k_cs.ct_cond, 1);
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}
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static void e2k_tr_insn_start(DisasContextBase *db, CPUState *cs)
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@ -436,8 +436,6 @@ static void e2k_tr_tb_stop(DisasContextBase *db, CPUState *cs)
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g_assert_not_reached();
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break;
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}
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tcg_temp_free(ctx->ct.cond);
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}
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static void e2k_tr_disas_log(const DisasContextBase *db, CPUState *cpu)
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@ -495,6 +493,7 @@ void e2k_tcg_initialize(void) {
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static const struct { TCGv *ptr; int off; const char *name; } rtl[] = {
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{ &e2k_cs.pc, offsetof(CPUE2KState, ip), "pc" },
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{ &e2k_cs.npc, offsetof(CPUE2KState, nip), "npc" },
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{ &e2k_cs.ct_cond, offsetof(CPUE2KState, ct_cond), "cond" },
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};
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unsigned int i;
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@ -58,6 +58,7 @@ typedef struct CPUE2KStateTCG {
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TCGv pc;
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TCGv npc;
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TCGv ctprs[4];
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TCGv ct_cond;
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TCGv_i64 lsr;
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TCGv_i64 wregs[WREGS_SIZE];
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TCGv_i64 gregs[GREGS_SIZE];
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@ -124,7 +125,6 @@ typedef enum {
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typedef struct {
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bool has_cond;
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TCGv cond;
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ControlTransferType type;
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union {
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target_ulong target;
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@ -546,7 +546,7 @@ static void execute_alopf_simple(DisasContext *dc, int chan)
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break;
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}
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case 0x40: // TODO: udivs used as temporary UD
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e2k_gen_exception(dc, E2K_EXCP_UNIMPL);
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e2k_gen_exception(dc, 0);
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break;
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case 0x61:
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if (chan == 2 || chan == 5) {
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@ -102,7 +102,7 @@ static inline void gen_cur_dec(DisasContext *ctx, TCGv_i32 ret, int cond,
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TCGv_i32 t0 = tcg_const_i32(n);
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(c, ctx->ct.cond);
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tcg_gen_trunc_tl_i32(c, e2k_cs.ct_cond);
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gen_helper_cur_dec(t1, cpu_env, cur, t0, size);
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gen_movcond_flag_i32(ret, cond, c, t1, cur);
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@ -126,7 +126,7 @@ void e2k_commit_stubs(DisasContext *ctx)
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TCGv_i64 t0 = tcg_temp_new_i64();
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gen_lcnt_dec(t0, e2k_cs.lsr);
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gen_movcond_flag_i64(e2k_cs.lsr, alc, ctx->ct.cond, t0, e2k_cs.lsr);
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gen_movcond_flag_i64(e2k_cs.lsr, alc, e2k_cs.ct_cond, t0, e2k_cs.lsr);
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tcg_temp_free_i64(t0);
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}
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@ -504,7 +504,7 @@ static void gen_jmp(DisasContext *dc)
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TCGv preg = tcg_temp_new();
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TCGv loop_end = tcg_temp_new();
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TCGv not_loop_end = tcg_temp_new();
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TCGv cond = dc->ct.cond;
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TCGv cond = e2k_cs.ct_cond;
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TCGv_i64 t0 = tcg_temp_new_i64();
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e2k_gen_preg(t0, psrc);
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