SPARC patches
HW: - Use UNIMP device instead of EMPTY_SLOT - Make EMPTY_SLOT similar to UNIMP device - Map UART devices unconditionally - Pair of fixes for AHB PnP - Add trace events to AHB PnP TCG: - Improve exception logging CI: - https://gitlab.com/philmd/qemu/-/pipelines/154231191 - https://travis-ci.org/github/philmd/qemu/builds/696321130 -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAl7fORkACgkQ4+MsLN6t wN56ExAAiWB10eKKbqYcsX6yHXXVmihRLbo0E4EbpeB9Vg8H2I3bhL3v4s/WCsKF zHL2uazLRFCjQMgy19UvuhDzXPgTZjhGAWvh2GhbB/B21WuXqNOsYj8OHkhUqNbg OFK2ZFDWcmK1ddnzJRxa2jG28Ei8TneO6DBRvECiT2r2IEmLuVUvc6Aacpzsqunj qZTAg4EnxUKKj1f0kPgaganPRa90ZWJlBNbLkBrbXw+xCZrja1HkKLH46NjRWoap 5jQznsCgKmKCnlYR1aDO/qGkj3W3VWqI4FPaP3v7p7GFqtOaQ8mu/wytv1uVvJRx P7+SkECNmVjIgbrsfG1cWHGvEZ5+iY0Au14/jG0Z/f3el4vgqjjxFBOXQtM4MOoO f9ANUQ9ecnlvSq9+P2Rst/CxlZNDEa/E/BANT0n4upYr8pPn9Ya1WrTtPIHYjQdv V5hhfNt78tqtGrJD68Z29ywZq8whfg2qwK1rpIZY5I3lyVaY/wfESAQit0HV6Lhf KL76nwvmSRxqIC88mChpUW6oGQLPJZW/s9Ug9pO4IzQo/ExoMvf9OOUmsk9Gctaq koTRCeoV4Wgcp+BkbCgHANKda9nGGfGanV0uJFBiclZAADfu9nmmdl9nEQoaPCxu fwocYIh2aYR9T2DgJvdOlkHLqzVeu9BPZpCKUhjyHE3AmETDsk0= =EHrR -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sparc-next-20200609' into staging SPARC patches HW: - Use UNIMP device instead of EMPTY_SLOT - Make EMPTY_SLOT similar to UNIMP device - Map UART devices unconditionally - Pair of fixes for AHB PnP - Add trace events to AHB PnP TCG: - Improve exception logging CI: - https://gitlab.com/philmd/qemu/-/pipelines/154231191 - https://travis-ci.org/github/philmd/qemu/builds/696321130 # gpg: Signature made Tue 09 Jun 2020 08:24:09 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/sparc-next-20200609: target/sparc/int32_helper: Extract and use excp_name_str() target/sparc/int32_helper: Remove DEBUG_PCALL definition hw/timer/grlib_gptimer: Display frequency in decimal hw/misc/grlib_ahb_apb_pnp: Add trace events on read accesses hw/misc/grlib_ahb_apb_pnp: Fix AHB PnP 8-bit accesses hw/misc/grlib_ahb_apb_pnp: Avoid crash when writing to AHB PnP registers hw/sparc64/niagara: Remove duplicated NIAGARA_UART_BASE definition hw/sparc64/niagara: Map the UART device unconditionally hw/sparc/leon3: Map the UART device unconditionally hw/misc/empty_slot: Name the slots when created hw/misc/empty_slot: Move the 'hw/misc' and cover in MAINTAINERS hw/misc/empty_slot: Convert debug printf() to trace event hw/misc/empty_slot: Add a 'name' qdev property hw/misc/empty_slot: Convert 'size' field as qdev property hw/misc/empty_slot: Lower address space priority hw/sparc/sun4m: Use UnimplementedDevice for I/O devices Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
31d321c2b3
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@ -1864,6 +1864,13 @@ S: Maintained
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F: include/hw/misc/unimp.h
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F: hw/misc/unimp.c
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Empty slot
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M: Artyom Tarasenko <atar4qemu@gmail.com>
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R: Philippe Mathieu-Daudé <f4bug@amsat.org>
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S: Maintained
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F: include/hw/misc/empty_slot.h
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F: hw/misc/empty_slot.c
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Standard VGA
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M: Gerd Hoffmann <kraxel@redhat.com>
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S: Maintained
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@ -24,7 +24,6 @@ common-obj-$(CONFIG_SOFTMMU) += numa.o
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common-obj-$(CONFIG_SOFTMMU) += clock-vmstate.o
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obj-$(CONFIG_SOFTMMU) += machine-qmp-cmds.o
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common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
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common-obj-$(CONFIG_XILINX_AXI) += stream.o
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common-obj-$(CONFIG_PTIMER) += ptimer.o
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common-obj-$(CONFIG_FITLOADER) += loader-fit.o
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@ -52,7 +52,7 @@
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#include "sysemu/runstate.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "hw/empty_slot.h"
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#include "hw/misc/empty_slot.h"
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#include "sysemu/kvm.h"
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#include "hw/semihosting/semihost.h"
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#include "hw/mips/cps.h"
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@ -1241,7 +1241,7 @@ void mips_malta_init(MachineState *machine)
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* exception when accessing invalid memory. Create an empty slot to
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* emulate this feature.
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*/
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empty_slot_init(0, 0x20000000);
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empty_slot_init("GT64120", 0, 0x20000000);
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qdev_init_nofail(dev);
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@ -10,6 +10,7 @@ common-obj-$(CONFIG_EDU) += edu.o
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common-obj-$(CONFIG_PCA9552) += pca9552.o
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common-obj-$(CONFIG_UNIMP) += unimp.o
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common-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
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common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o
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# ARM devices
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@ -11,17 +11,9 @@
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qemu/module.h"
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#include "hw/empty_slot.h"
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//#define DEBUG_EMPTY_SLOT
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#ifdef DEBUG_EMPTY_SLOT
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#define DPRINTF(fmt, ...) \
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do { printf("empty_slot: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF(fmt, ...) do {} while (0)
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#endif
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#include "hw/qdev-properties.h"
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#include "hw/misc/empty_slot.h"
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#include "trace.h"
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#define TYPE_EMPTY_SLOT "empty_slot"
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#define EMPTY_SLOT(obj) OBJECT_CHECK(EmptySlot, (obj), TYPE_EMPTY_SLOT)
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@ -30,20 +22,26 @@ typedef struct EmptySlot {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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char *name;
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uint64_t size;
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} EmptySlot;
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static uint64_t empty_slot_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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DPRINTF("read from " TARGET_FMT_plx "\n", addr);
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EmptySlot *s = EMPTY_SLOT(opaque);
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trace_empty_slot_write(addr, size << 1, 0, size, s->name);
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return 0;
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}
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static void empty_slot_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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DPRINTF("write 0x%x to " TARGET_FMT_plx "\n", (unsigned)val, addr);
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EmptySlot *s = EMPTY_SLOT(opaque);
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trace_empty_slot_write(addr, size << 1, val, size, s->name);
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}
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static const MemoryRegionOps empty_slot_ops = {
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@ -52,22 +50,18 @@ static const MemoryRegionOps empty_slot_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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void empty_slot_init(hwaddr addr, uint64_t slot_size)
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void empty_slot_init(const char *name, hwaddr addr, uint64_t slot_size)
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{
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if (slot_size > 0) {
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/* Only empty slots larger than 0 byte need handling. */
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DeviceState *dev;
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SysBusDevice *s;
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EmptySlot *e;
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dev = qdev_create(NULL, TYPE_EMPTY_SLOT);
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s = SYS_BUS_DEVICE(dev);
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e = EMPTY_SLOT(dev);
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e->size = slot_size;
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qdev_prop_set_uint64(dev, "size", slot_size);
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qdev_init_nofail(dev);
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sysbus_mmio_map(s, 0, addr);
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sysbus_mmio_map_overlap(SYS_BUS_DEVICE(dev), 0, addr, -10000);
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}
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}
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@ -75,16 +69,27 @@ static void empty_slot_realize(DeviceState *dev, Error **errp)
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{
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EmptySlot *s = EMPTY_SLOT(dev);
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if (s->name == NULL) {
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s->name = g_strdup("empty-slot");
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}
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memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s,
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"empty-slot", s->size);
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s->name, s->size);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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}
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static Property empty_slot_properties[] = {
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DEFINE_PROP_UINT64("size", EmptySlot, size, 0),
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DEFINE_PROP_STRING("name", EmptySlot, name),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void empty_slot_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = empty_slot_realize;
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device_class_set_props(dc, empty_slot_properties);
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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}
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static const TypeInfo empty_slot_info = {
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@ -25,6 +25,7 @@
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#include "qemu/log.h"
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#include "hw/sysbus.h"
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#include "hw/misc/grlib_ahb_apb_pnp.h"
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#include "trace.h"
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#define GRLIB_PNP_VENDOR_SHIFT (24)
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#define GRLIB_PNP_VENDOR_SIZE (8)
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@ -132,13 +133,28 @@ void grlib_ahb_pnp_add_entry(AHBPnp *dev, uint32_t address, uint32_t mask,
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static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
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{
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AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
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uint32_t val;
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return ahb_pnp->regs[offset >> 2];
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val = ahb_pnp->regs[offset >> 2];
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trace_grlib_ahb_pnp_read(offset, val);
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return val;
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}
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static void grlib_ahb_pnp_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
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}
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static const MemoryRegionOps grlib_ahb_pnp_ops = {
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.read = grlib_ahb_pnp_read,
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.write = grlib_ahb_pnp_write,
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.endianness = DEVICE_BIG_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp)
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@ -228,8 +244,12 @@ void grlib_apb_pnp_add_entry(APBPnp *dev, uint32_t address, uint32_t mask,
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static uint64_t grlib_apb_pnp_read(void *opaque, hwaddr offset, unsigned size)
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{
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APBPnp *apb_pnp = GRLIB_APB_PNP(opaque);
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uint32_t val;
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return apb_pnp->regs[offset >> 2];
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val = apb_pnp->regs[offset >> 2];
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trace_grlib_apb_pnp_read(offset, val);
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return val;
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}
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static void grlib_apb_pnp_write(void *opaque, hwaddr addr,
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@ -39,6 +39,10 @@ ecc_mem_readl_ecr1(uint32_t ret) "Read event count 2 0x%08x"
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ecc_diag_mem_writeb(uint64_t addr, uint32_t val) "Write diagnostic %"PRId64" = 0x%02x"
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ecc_diag_mem_readb(uint64_t addr, uint32_t ret) "Read diagnostic %"PRId64"= 0x%02x"
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# empty_slot.c
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empty_slot_read(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "rd addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]"
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empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "wr addr:0x%04"PRIx64" data:0x%0*"PRIx64" size %u [%s]"
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# slavio_misc.c
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slavio_misc_update_irq_raise(void) "Raise IRQ"
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slavio_misc_update_irq_lower(void) "Lower IRQ"
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@ -198,3 +202,7 @@ via1_rtc_cmd_pram_read(int addr, int value) "addr=%u value=0x%02x"
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via1_rtc_cmd_pram_write(int addr, int value) "addr=%u value=0x%02x"
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via1_rtc_cmd_pram_sect_read(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=%d value=0x%02x"
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via1_rtc_cmd_pram_sect_write(int sector, int offset, int addr, int value) "sector=%u offset=%u addr=%d value=0x%02x"
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# grlib_ahb_apb_pnp.c
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grlib_ahb_pnp_read(uint64_t addr, uint32_t value) "AHB PnP read addr:0x%03"PRIx64" data:0x%08x"
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grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03"PRIx64" data:0x%08x"
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@ -5,6 +5,7 @@ config SUN4M
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select CS4231
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select ECCMEMCTL
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select EMPTY_SLOT
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select UNIMP
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select ESCC
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select ESP
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select FDC
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@ -339,16 +339,14 @@ static void leon3_generic_hw_init(MachineState *machine)
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0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
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/* Allocate uart */
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if (serial_hd(0)) {
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dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
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qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
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LEON3_UART_IRQ, GRLIB_APBIO_AREA);
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}
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dev = qdev_create(NULL, TYPE_GRLIB_APB_UART);
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qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irqs[LEON3_UART_IRQ]);
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grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
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GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
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LEON3_UART_IRQ, GRLIB_APBIO_AREA);
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}
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static void leon3_generic_machine_init(MachineClass *mc)
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|
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@ -46,7 +46,8 @@
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#include "hw/nvram/chrp_nvram.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/char/escc.h"
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#include "hw/empty_slot.h"
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#include "hw/misc/empty_slot.h"
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#include "hw/misc/unimp.h"
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#include "hw/irq.h"
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#include "hw/loader.h"
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#include "elf.h"
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|
|
@ -883,7 +884,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
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|
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/* models without ECC don't trap when missing ram is accessed */
|
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if (!hwdef->ecc_base) {
|
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empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
|
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empty_slot_init("ecc", machine->ram_size,
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hwdef->max_mem - machine->ram_size);
|
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}
|
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|
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prom_init(hwdef->slavio_base, bios_name);
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|
|
@ -914,7 +916,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
|
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Software shouldn't use aliased addresses, neither should it crash
|
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when does. Using empty_slot instead of aliasing can help with
|
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debugging such accesses */
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empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
|
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empty_slot_init("iommu.alias",
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hwdef->iommu_pad_base, hwdef->iommu_pad_len);
|
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}
|
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|
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sparc32_dma_init(hwdef->dma_base,
|
||||
|
|
@ -963,12 +966,14 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
|
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for (i = 0; i < MAX_VSIMMS; i++) {
|
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/* vsimm registers probed by OBP */
|
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if (hwdef->vsimm[i].reg_base) {
|
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empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
|
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char *name = g_strdup_printf("vsimm[%d]", i);
|
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empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000);
|
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g_free(name);
|
||||
}
|
||||
}
|
||||
|
||||
if (hwdef->sx_base) {
|
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empty_slot_init(hwdef->sx_base, 0x2000);
|
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create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000);
|
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}
|
||||
|
||||
nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
|
||||
|
|
@ -1031,14 +1036,16 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
|
|||
if (hwdef->dbri_base) {
|
||||
/* ISDN chip with attached CS4215 audio codec */
|
||||
/* prom space */
|
||||
empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
|
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create_unimplemented_device("SUNW,DBRI.prom",
|
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hwdef->dbri_base + 0x1000, 0x30);
|
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/* reg space */
|
||||
empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
|
||||
create_unimplemented_device("SUNW,DBRI",
|
||||
hwdef->dbri_base + 0x10000, 0x100);
|
||||
}
|
||||
|
||||
if (hwdef->bpp_base) {
|
||||
/* parallel port */
|
||||
empty_slot_init(hwdef->bpp_base, 0x20);
|
||||
create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20);
|
||||
}
|
||||
|
||||
initrd_size = 0;
|
||||
|
|
|
|||
|
|
@ -68,7 +68,6 @@ typedef struct NiagaraBoardState {
|
|||
|
||||
#define NIAGARA_VDISK_BASE 0x1f40000000ULL
|
||||
#define NIAGARA_RTC_BASE 0xfff0c1fff8ULL
|
||||
#define NIAGARA_UART_BASE 0x1f10000000ULL
|
||||
|
||||
/* Firmware layout
|
||||
*
|
||||
|
|
@ -152,10 +151,8 @@ static void niagara_init(MachineState *machine)
|
|||
exit(1);
|
||||
}
|
||||
}
|
||||
if (serial_hd(0)) {
|
||||
serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
|
||||
serial_hd(0), DEVICE_BIG_ENDIAN);
|
||||
}
|
||||
serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL,
|
||||
115200, serial_hd(0), DEVICE_BIG_ENDIAN);
|
||||
create_unimplemented_device("sun4v-iob", NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
|
||||
sun4v_rtc_init(NIAGARA_RTC_BASE);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ slavio_timer_mem_writel_invalid(uint64_t addr) "invalid write address 0x%"PRIx64
|
|||
grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run"
|
||||
grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x"
|
||||
grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
|
||||
grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq: 0x%x"
|
||||
grlib_gptimer_set_scaler(uint32_t scaler, uint32_t freq) "scaler:0x%x freq:%uHz"
|
||||
grlib_gptimer_hit(int id) "timer:%d HIT"
|
||||
grlib_gptimer_readl(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
|
||||
grlib_gptimer_writel(int id, uint64_t addr, uint32_t val) "timer:%d addr 0x%"PRIx64" 0x%x"
|
||||
|
|
|
|||
|
|
@ -1,9 +0,0 @@
|
|||
#ifndef HW_EMPTY_SLOT_H
|
||||
#define HW_EMPTY_SLOT_H
|
||||
|
||||
#include "exec/hwaddr.h"
|
||||
|
||||
/* empty_slot.c */
|
||||
void empty_slot_init(hwaddr addr, uint64_t slot_size);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* QEMU Empty Slot
|
||||
*
|
||||
* The empty_slot device emulates known to a bus but not connected devices.
|
||||
*
|
||||
* Copyright (c) 2010 Artyom Tarasenko
|
||||
*
|
||||
* This code is licensed under the GNU GPL v2 or (at your option) any later
|
||||
* version.
|
||||
*/
|
||||
|
||||
#ifndef HW_EMPTY_SLOT_H
|
||||
#define HW_EMPTY_SLOT_H
|
||||
|
||||
#include "exec/hwaddr.h"
|
||||
|
||||
void empty_slot_init(const char *name, hwaddr addr, uint64_t slot_size);
|
||||
|
||||
#endif
|
||||
|
|
@ -23,9 +23,7 @@
|
|||
#include "exec/log.h"
|
||||
#include "sysemu/runstate.h"
|
||||
|
||||
#define DEBUG_PCALL
|
||||
|
||||
#ifdef DEBUG_PCALL
|
||||
static const char * const excp_names[0x80] = {
|
||||
[TT_TFAULT] = "Instruction Access Fault",
|
||||
[TT_ILL_INSN] = "Illegal Instruction",
|
||||
|
|
@ -58,7 +56,14 @@ static const char * const excp_names[0x80] = {
|
|||
[TT_DIV_ZERO] = "Division By Zero",
|
||||
[TT_NCP_INSN] = "Coprocessor Disabled",
|
||||
};
|
||||
#endif
|
||||
|
||||
static const char *excp_name_str(int32_t exception_index)
|
||||
{
|
||||
if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) {
|
||||
return "Unknown";
|
||||
}
|
||||
return excp_names[exception_index];
|
||||
}
|
||||
|
||||
void sparc_cpu_do_interrupt(CPUState *cs)
|
||||
{
|
||||
|
|
@ -71,7 +76,6 @@ void sparc_cpu_do_interrupt(CPUState *cs)
|
|||
cpu_get_psr(env);
|
||||
}
|
||||
|
||||
#ifdef DEBUG_PCALL
|
||||
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
||||
static int count;
|
||||
const char *name;
|
||||
|
|
@ -81,10 +85,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
|
|||
} else if (intno >= 0x80) {
|
||||
name = "Trap Instruction";
|
||||
} else {
|
||||
name = excp_names[intno];
|
||||
if (!name) {
|
||||
name = "Unknown";
|
||||
}
|
||||
name = excp_name_str(intno);
|
||||
}
|
||||
|
||||
qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
|
||||
|
|
@ -104,15 +105,15 @@ void sparc_cpu_do_interrupt(CPUState *cs)
|
|||
#endif
|
||||
count++;
|
||||
}
|
||||
#endif
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
if (env->psret == 0) {
|
||||
if (cs->exception_index == 0x80 &&
|
||||
env->def.features & CPU_FEATURE_TA0_SHUTDOWN) {
|
||||
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
|
||||
} else {
|
||||
cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",
|
||||
cs->exception_index);
|
||||
cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
|
||||
"Error state",
|
||||
cs->exception_index, excp_name_str(cs->exception_index));
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue