OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target-mips/dsp_helper.c: Add ifdef guards around various functions

Browse Source 
Add ifdef TARGET_MIPS64 guards around various functions that are only
called from helpers for TARGET_MIPS64 CPUs; this avoids compiler
warnings when building other configs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Peter Maydell 2014-09-14 20:45:36 +01:00 committed by Leon Alrae
parent c7986fd6cd
commit 31efecccce
1 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
target-mips/dsp_helper.c
View File

@ -274,6 +274,7 @@ static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
return result; return result;
} }
#ifdef TARGET_MIPS64
/* a[0] is LO, a[1] is HI. */ /* a[0] is LO, a[1] is HI. */
static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret, static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
int32_t ac, int32_t ac,
@ -327,6 +328,7 @@ static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
set_DSPControl_overflow_flag(1, 16 + ac, env); set_DSPControl_overflow_flag(1, 16 + ac, env);
} }
} }
#endif
static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b, static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
CPUMIPSState *env) CPUMIPSState *env)
@ -348,10 +350,12 @@ static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
return a * b; return a * b;
} }
#ifdef TARGET_MIPS64
static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b) static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
{ {
return a * b; return a * b;
} }
#endif
static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b, static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
CPUMIPSState *env) CPUMIPSState *env)
@ -408,10 +412,12 @@ static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
return a >> mov; return a >> mov;
} }
#ifdef TARGET_MIPS64
static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov) static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
{ {
return a >> mov; return a >> mov;
} }
#endif
static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b) static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
{ {
@ -470,6 +476,7 @@ static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
return (temp >> 1) & 0x00FF; return (temp >> 1) & 0x00FF;
} }
#ifdef TARGET_MIPS64
static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b) static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
{ {
uint16_t temp; uint16_t temp;
@ -487,6 +494,7 @@ static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
return (temp >> 1) & 0x00FF; return (temp >> 1) & 0x00FF;
} }
#endif
/* 128 bits long. p[0] is LO, p[1] is HI. */ /* 128 bits long. p[0] is LO, p[1] is HI. */
static inline void mipsdsp_rndrashift_short_acc(int64_t *p, static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
@ -502,6 +510,7 @@ static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
p[1] = (acc >> 63) & 0x01; p[1] = (acc >> 63) & 0x01;
} }
#ifdef TARGET_MIPS64
/* 128 bits long. p[0] is LO, p[1] is HI */ /* 128 bits long. p[0] is LO, p[1] is HI */
static inline void mipsdsp_rashift_acc(uint64_t *p, static inline void mipsdsp_rashift_acc(uint64_t *p,
uint32_t ac, uint32_t ac,
@ -549,6 +558,7 @@ static inline void mipsdsp_rndrashift_acc(uint64_t *p,
} }
} }
} }
#endif
static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b, static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
CPUMIPSState *env) CPUMIPSState *env)
@ -599,10 +609,12 @@ static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
return tempI & 0x0000FFFF; return tempI & 0x0000FFFF;
} }
#ifdef TARGET_MIPS64
static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b) static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
{ {
return (uint64_t)a * (uint64_t)b; return (uint64_t)a * (uint64_t)b;
} }
#endif
static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b, static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
CPUMIPSState *env) CPUMIPSState *env)
@ -708,7 +720,7 @@ static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
return a << s; return a << s;
} }
#ifdef TARGET_MIPS64
static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s, static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
CPUMIPSState *env) CPUMIPSState *env)
{ {
@ -725,6 +737,7 @@ static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
return a << s; return a << s;
} }
} }
#endif
static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s, static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
CPUMIPSState *env) CPUMIPSState *env)
@ -964,6 +977,7 @@ static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
return temp & 0x00FF; return temp & 0x00FF;
} }
#ifdef TARGET_MIPS64
static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env) static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
{ {
int32_t temp; int32_t temp;
@ -988,6 +1002,7 @@ static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
return temp; return temp;
} }
#endif
static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b) static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
{ {