tcg: Remove needless CPUState::current_tb

This field was used for telling cpu_interrupt() to unlink a chain of TBs
being executed when it worked that way. Now, cpu_interrupt() don't do
this anymore. So we don't need this field anymore.

Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com>
Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org>
Message-Id: <1462273462-14036-1-git-send-email-sergey.fedorov@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Sergey Fedorov 2016-05-03 14:04:22 +03:00 committed by Richard Henderson
parent a0522c7a55
commit 3213525f8a
7 changed files with 2 additions and 41 deletions

View File

@ -68,7 +68,6 @@ void cpu_reloading_memory_map(void)
void cpu_loop_exit(CPUState *cpu) void cpu_loop_exit(CPUState *cpu)
{ {
cpu->current_tb = NULL;
siglongjmp(cpu->jmp_env, 1); siglongjmp(cpu->jmp_env, 1);
} }
@ -77,6 +76,5 @@ void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc)
if (pc) { if (pc) {
cpu_restore_state(cpu, pc); cpu_restore_state(cpu, pc);
} }
cpu->current_tb = NULL;
siglongjmp(cpu->jmp_env, 1); siglongjmp(cpu->jmp_env, 1);
} }

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@ -216,11 +216,9 @@ static void cpu_exec_nocache(CPUState *cpu, int max_cycles,
| (ignore_icount ? CF_IGNORE_ICOUNT : 0)); | (ignore_icount ? CF_IGNORE_ICOUNT : 0));
tb->orig_tb = cpu->tb_flushed ? NULL : orig_tb; tb->orig_tb = cpu->tb_flushed ? NULL : orig_tb;
cpu->tb_flushed |= old_tb_flushed; cpu->tb_flushed |= old_tb_flushed;
cpu->current_tb = tb;
/* execute the generated code */ /* execute the generated code */
trace_exec_tb_nocache(tb, tb->pc); trace_exec_tb_nocache(tb, tb->pc);
cpu_tb_exec(cpu, tb); cpu_tb_exec(cpu, tb);
cpu->current_tb = NULL;
tb_phys_invalidate(tb, -1); tb_phys_invalidate(tb, -1);
tb_free(tb); tb_free(tb);
} }
@ -532,9 +530,7 @@ int cpu_exec(CPUState *cpu)
uintptr_t ret; uintptr_t ret;
trace_exec_tb(tb, tb->pc); trace_exec_tb(tb, tb->pc);
/* execute the generated code */ /* execute the generated code */
cpu->current_tb = tb;
ret = cpu_tb_exec(cpu, tb); ret = cpu_tb_exec(cpu, tb);
cpu->current_tb = NULL;
last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK); last_tb = (TranslationBlock *)(ret & ~TB_EXIT_MASK);
tb_exit = ret & TB_EXIT_MASK; tb_exit = ret & TB_EXIT_MASK;
switch (tb_exit) { switch (tb_exit) {

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@ -76,10 +76,6 @@ void tlb_flush(CPUState *cpu, int flush_global)
tlb_debug("(%d)\n", flush_global); tlb_debug("(%d)\n", flush_global);
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
cpu->current_tb = NULL;
memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_table, -1, sizeof(env->tlb_table));
memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
@ -95,9 +91,6 @@ static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp)
CPUArchState *env = cpu->env_ptr; CPUArchState *env = cpu->env_ptr;
tlb_debug("start\n"); tlb_debug("start\n");
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
cpu->current_tb = NULL;
for (;;) { for (;;) {
int mmu_idx = va_arg(argp, int); int mmu_idx = va_arg(argp, int);
@ -152,9 +145,6 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
tlb_flush(cpu, 1); tlb_flush(cpu, 1);
return; return;
} }
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
cpu->current_tb = NULL;
addr &= TARGET_PAGE_MASK; addr &= TARGET_PAGE_MASK;
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
@ -193,9 +183,6 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
va_end(argp); va_end(argp);
return; return;
} }
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
cpu->current_tb = NULL;
addr &= TARGET_PAGE_MASK; addr &= TARGET_PAGE_MASK;
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);

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@ -446,7 +446,6 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
resume_all_vcpus(); resume_all_vcpus();
if (!kvm_enabled()) { if (!kvm_enabled()) {
cs->current_tb = NULL;
tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1); tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(cs, NULL); cpu_resume_from_signal(cs, NULL);
} }

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@ -253,7 +253,6 @@ struct kvm_run;
* @as: Pointer to the first AddressSpace, for the convenience of targets which * @as: Pointer to the first AddressSpace, for the convenience of targets which
* only have a single AddressSpace * only have a single AddressSpace
* @env_ptr: Pointer to subclass-specific CPUArchState field. * @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
* @gdb_regs: Additional GDB registers. * @gdb_regs: Additional GDB registers.
* @gdb_num_regs: Number of total registers accessible to GDB. * @gdb_num_regs: Number of total registers accessible to GDB.
* @gdb_num_g_regs: Number of registers in GDB 'g' packets. * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
@ -305,7 +304,6 @@ struct CPUState {
MemoryRegion *memory; MemoryRegion *memory;
void *env_ptr; /* CPUArchState */ void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
struct GDBRegisterState *gdb_regs; struct GDBRegisterState *gdb_regs;
int gdb_num_regs; int gdb_num_regs;

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@ -254,7 +254,6 @@ static void cpu_common_reset(CPUState *cpu)
} }
cpu->interrupt_request = 0; cpu->interrupt_request = 0;
cpu->current_tb = NULL;
cpu->halted = 0; cpu->halted = 0;
cpu->mem_io_pc = 0; cpu->mem_io_pc = 0;
cpu->mem_io_vaddr = 0; cpu->mem_io_vaddr = 0;

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@ -305,7 +305,6 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
cpu_restore_state_from_tb(cpu, tb, retaddr); cpu_restore_state_from_tb(cpu, tb, retaddr);
if (tb->cflags & CF_NOCACHE) { if (tb->cflags & CF_NOCACHE) {
/* one-shot translation, invalidate it immediately */ /* one-shot translation, invalidate it immediately */
cpu->current_tb = NULL;
tb_phys_invalidate(tb, -1); tb_phys_invalidate(tb, -1);
tb_free(tb); tb_free(tb);
} }
@ -1309,9 +1308,9 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end)
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access) int is_cpu_write_access)
{ {
TranslationBlock *tb, *tb_next, *saved_tb; TranslationBlock *tb, *tb_next;
CPUState *cpu = current_cpu;
#if defined(TARGET_HAS_PRECISE_SMC) #if defined(TARGET_HAS_PRECISE_SMC)
CPUState *cpu = current_cpu;
CPUArchState *env = NULL; CPUArchState *env = NULL;
#endif #endif
tb_page_addr_t tb_start, tb_end; tb_page_addr_t tb_start, tb_end;
@ -1378,20 +1377,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
&current_flags); &current_flags);
} }
#endif /* TARGET_HAS_PRECISE_SMC */ #endif /* TARGET_HAS_PRECISE_SMC */
/* we need to do that to handle the case where a signal
occurs while doing tb_phys_invalidate() */
saved_tb = NULL;
if (cpu != NULL) {
saved_tb = cpu->current_tb;
cpu->current_tb = NULL;
}
tb_phys_invalidate(tb, -1); tb_phys_invalidate(tb, -1);
if (cpu != NULL) {
cpu->current_tb = saved_tb;
if (cpu->interrupt_request && cpu->current_tb) {
cpu_interrupt(cpu, cpu->interrupt_request);
}
}
} }
tb = tb_next; tb = tb_next;
} }
@ -1407,7 +1393,6 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
/* we generate a block containing just the instruction /* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify modifying the memory. It will ensure that it cannot modify
itself */ itself */
cpu->current_tb = NULL;
tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(cpu, NULL); cpu_resume_from_signal(cpu, NULL);
} }
@ -1512,7 +1497,6 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
/* we generate a block containing just the instruction /* we generate a block containing just the instruction
modifying the memory. It will ensure that it cannot modify modifying the memory. It will ensure that it cannot modify
itself */ itself */
cpu->current_tb = NULL;
tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
if (locked) { if (locked) {
mmap_unlock(); mmap_unlock();