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hw/arm/armsse: Allow boards to specify init-svtor

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The Musca boards have DAPLink firmware that sets the initial
secure VTOR value (the location of the vector table) differently
depending on the boot mode (from flash, from RAM, etc). Export
the init-svtor as a QOM property of the ARMSSE object so that
the board can change it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2019-02-21 18:17:47 +00:00
parent 74ecf7677b
commit 321874196d
2 changed files with 7 additions and 4 deletions
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8
hw/arm/armsse.c
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@ -505,11 +505,10 @@ static void armsse_realize(DeviceState *dev, Error **errp)
* the INITSVTOR* registers before powering up the CPUs in any case, * the INITSVTOR* registers before powering up the CPUs in any case,
* so the hardware's default value doesn't matter. QEMU doesn't emulate * so the hardware's default value doesn't matter. QEMU doesn't emulate
* the control processor, so instead we behave in the way that the * the control processor, so instead we behave in the way that the
* firmware does. All boards currently known about have firmware that * firmware does. The initial value is configurable by the board code
* sets the INITSVTOR0 and INITSVTOR1 registers to 0x10000000, like the * to match whatever its firmware does.
* IoTKit default. We can make this more configurable if necessary.
*/ */
qdev_prop_set_uint32(cpudev, "init-svtor", 0x10000000); qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
/* /*
* Start all CPUs except CPU0 powered down. In real hardware it is * Start all CPUs except CPU0 powered down. In real hardware it is
* a configurable property of the SSE-200 which CPUs start powered up * a configurable property of the SSE-200 which CPUs start powered up
@ -1187,6 +1186,7 @@ static Property armsse_properties[] = {
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64), DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0), DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15), DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_UINT32("init-svtor", ARMSSE, init_svtor, 0x10000000),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };

3
include/hw/arm/armsse.h
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@ -48,6 +48,8 @@
* if necessary.) * if necessary.)
* + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the * + QOM property "SRAM_ADDR_WIDTH" sets the number of bits used for the
* address of each SRAM bank (and thus the total amount of internal SRAM) * address of each SRAM bank (and thus the total amount of internal SRAM)
* + QOM property "init-svtor" sets the initial value of the CPU SVTOR register
* (where it expects to load the PC and SP from the vector table on reset)
* + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0, * + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts for CPU 0,
* which are wired to its NVIC lines 32 .. n+32 * which are wired to its NVIC lines 32 .. n+32
* + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for * + Named GPIO inputs "EXP_CPU1_IRQ" 0..n are the expansion interrupts for
@ -204,6 +206,7 @@ typedef struct ARMSSE {
uint32_t exp_numirq; uint32_t exp_numirq;
uint32_t mainclk_frq; uint32_t mainclk_frq;
uint32_t sram_addr_width; uint32_t sram_addr_width;
uint32_t init_svtor;
} ARMSSE; } ARMSSE;
typedef struct ARMSSEInfo ARMSSEInfo; typedef struct ARMSSEInfo ARMSSEInfo;