target-mips: change interrupt bits to be mips16-aware
We need to stash the operating mode into the low bit of the error PC and restore it on return from interrupts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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32188a03da
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@ -369,6 +369,24 @@ static const char * const excp_names[EXCP_LAST + 1] = {
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[EXCP_CACHE] = "cache error",
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[EXCP_CACHE] = "cache error",
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};
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};
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#if !defined(CONFIG_USER_ONLY)
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static target_ulong exception_resume_pc (CPUState *env)
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{
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target_ulong bad_pc;
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target_ulong isa_mode;
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isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
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bad_pc = env->active_tc.PC | isa_mode;
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot, come back to
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the jump. */
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bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
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}
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return bad_pc;
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}
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#endif
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void do_interrupt (CPUState *env)
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void do_interrupt (CPUState *env)
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{
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{
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#if !defined(CONFIG_USER_ONLY)
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#if !defined(CONFIG_USER_ONLY)
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@ -396,7 +414,7 @@ void do_interrupt (CPUState *env)
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resume will always occur on the next instruction
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resume will always occur on the next instruction
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(but we assume the pc has always been updated during
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(but we assume the pc has always been updated during
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code translation). */
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code translation). */
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env->CP0_DEPC = env->active_tc.PC;
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env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
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goto enter_debug_mode;
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goto enter_debug_mode;
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case EXCP_DINT:
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case EXCP_DINT:
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env->CP0_Debug |= 1 << CP0DB_DINT;
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env->CP0_Debug |= 1 << CP0DB_DINT;
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@ -413,14 +431,8 @@ void do_interrupt (CPUState *env)
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case EXCP_DDBL:
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case EXCP_DDBL:
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env->CP0_Debug |= 1 << CP0DB_DDBL;
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env->CP0_Debug |= 1 << CP0DB_DDBL;
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set_DEPC:
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set_DEPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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env->CP0_DEPC = exception_resume_pc(env);
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_DEPC = env->active_tc.PC - 4;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_DEPC = env->active_tc.PC;
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}
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enter_debug_mode:
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enter_debug_mode:
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env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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env->hflags &= ~(MIPS_HFLAG_KSU);
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@ -428,6 +440,8 @@ void do_interrupt (CPUState *env)
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00480;
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env->active_tc.PC = (int32_t)0xBFC00480;
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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break;
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break;
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case EXCP_RESET:
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case EXCP_RESET:
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cpu_reset(env);
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cpu_reset(env);
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@ -439,20 +453,16 @@ void do_interrupt (CPUState *env)
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case EXCP_NMI:
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case EXCP_NMI:
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env->CP0_Status |= (1 << CP0St_NMI);
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env->CP0_Status |= (1 << CP0St_NMI);
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set_error_EPC:
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set_error_EPC:
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if (env->hflags & MIPS_HFLAG_BMASK) {
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env->CP0_ErrorEPC = exception_resume_pc(env);
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_ErrorEPC = env->active_tc.PC - 4;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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env->hflags &= ~MIPS_HFLAG_BMASK;
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} else {
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env->CP0_ErrorEPC = env->active_tc.PC;
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}
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
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env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
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env->hflags &= ~(MIPS_HFLAG_KSU);
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env->hflags &= ~(MIPS_HFLAG_KSU);
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00000;
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env->active_tc.PC = (int32_t)0xBFC00000;
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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break;
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break;
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case EXCP_EXT_INTERRUPT:
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case EXCP_EXT_INTERRUPT:
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cause = 0;
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cause = 0;
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@ -554,13 +564,10 @@ void do_interrupt (CPUState *env)
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}
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}
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set_EPC:
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set_EPC:
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if (!(env->CP0_Status & (1 << CP0St_EXL))) {
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if (!(env->CP0_Status & (1 << CP0St_EXL))) {
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env->CP0_EPC = exception_resume_pc(env);
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if (env->hflags & MIPS_HFLAG_BMASK) {
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if (env->hflags & MIPS_HFLAG_BMASK) {
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/* If the exception was raised from a delay slot,
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come back to the jump. */
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env->CP0_EPC = env->active_tc.PC - 4;
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env->CP0_Cause |= (1 << CP0Ca_BD);
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env->CP0_Cause |= (1 << CP0Ca_BD);
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} else {
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} else {
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env->CP0_EPC = env->active_tc.PC;
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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}
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}
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env->CP0_Status |= (1 << CP0St_EXL);
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env->CP0_Status |= (1 << CP0St_EXL);
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@ -574,6 +581,8 @@ void do_interrupt (CPUState *env)
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env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
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env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
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}
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}
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env->active_tc.PC += offset;
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env->active_tc.PC += offset;
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
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env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
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break;
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break;
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default:
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default:
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@ -1684,14 +1684,24 @@ static void debug_post_eret (void)
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}
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}
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}
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}
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static void set_pc (target_ulong error_pc)
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{
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env->active_tc.PC = error_pc & ~(target_ulong)1;
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if (error_pc & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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} else {
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env->hflags &= ~(MIPS_HFLAG_M16);
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}
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}
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void helper_eret (void)
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void helper_eret (void)
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{
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{
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debug_pre_eret();
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debug_pre_eret();
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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if (env->CP0_Status & (1 << CP0St_ERL)) {
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env->active_tc.PC = env->CP0_ErrorEPC;
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set_pc(env->CP0_ErrorEPC);
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env->CP0_Status &= ~(1 << CP0St_ERL);
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env->CP0_Status &= ~(1 << CP0St_ERL);
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} else {
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} else {
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env->active_tc.PC = env->CP0_EPC;
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set_pc(env->CP0_EPC);
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env->CP0_Status &= ~(1 << CP0St_EXL);
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env->CP0_Status &= ~(1 << CP0St_EXL);
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}
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}
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compute_hflags(env);
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compute_hflags(env);
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@ -1702,7 +1712,8 @@ void helper_eret (void)
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void helper_deret (void)
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void helper_deret (void)
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{
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{
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debug_pre_eret();
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debug_pre_eret();
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env->active_tc.PC = env->CP0_DEPC;
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set_pc(env->CP0_DEPC);
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env->hflags &= MIPS_HFLAG_DM;
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env->hflags &= MIPS_HFLAG_DM;
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compute_hflags(env);
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compute_hflags(env);
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debug_post_eret();
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debug_post_eret();
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