target/sparc: Split out fp ldst functions with asi precomputed
Take the operation size from the MemOp instead of a separate parameter. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
5458fd3153
commit
3259b9e2fd
@ -2320,35 +2320,41 @@ static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
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}
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}
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static void __attribute__((unused))
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gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
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TCGv addr, int rd)
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{
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DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
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MemOp memop = da->memop;
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MemOp size = memop & MO_SIZE;
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TCGv_i32 d32;
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TCGv_i64 d64;
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switch (da.type) {
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/* TODO: Use 128-bit load/store below. */
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if (size == MO_128) {
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memop = (memop & ~MO_SIZE) | MO_64;
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}
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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memop |= MO_ALIGN_4;
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switch (size) {
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case 4:
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case MO_32:
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d32 = gen_dest_fpr_F(dc);
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tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
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tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop);
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gen_store_fpr_F(dc, rd, d32);
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break;
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case 8:
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
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da.memop | MO_ALIGN_4);
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case MO_64:
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop);
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break;
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case 16:
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case MO_128:
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d64 = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4);
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tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx,
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da.memop | MO_ALIGN_4);
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop);
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tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
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break;
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default:
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@ -2358,24 +2364,19 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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case GET_ASI_BLOCK:
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/* Valid for lddfa on aligned registers only. */
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if (size == 8 && (rd & 7) == 0) {
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MemOp memop;
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if (orig_size == MO_64 && (rd & 7) == 0) {
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TCGv eight;
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int i;
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gen_address_mask(dc, addr);
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/* The first operation checks required alignment. */
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memop = da.memop | MO_ALIGN_64;
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eight = tcg_constant_tl(8);
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for (i = 0; ; ++i) {
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr,
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da.mem_idx, memop);
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
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memop | (i == 0 ? MO_ALIGN_64 : 0));
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if (i == 7) {
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break;
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}
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tcg_gen_add_tl(addr, addr, eight);
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memop = da.memop;
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}
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} else {
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gen_exception(dc, TT_ILL_INSN);
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@ -2384,10 +2385,9 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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case GET_ASI_SHORT:
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/* Valid for lddfa only. */
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if (size == 8) {
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gen_address_mask(dc, addr);
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
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da.memop | MO_ALIGN);
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if (orig_size == MO_64) {
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tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN);
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} else {
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gen_exception(dc, TT_ILL_INSN);
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}
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@ -2395,8 +2395,8 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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default:
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{
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TCGv_i32 r_asi = tcg_constant_i32(da.asi);
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TCGv_i32 r_mop = tcg_constant_i32(da.memop | MO_ALIGN);
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TCGv_i32 r_asi = tcg_constant_i32(da->asi);
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TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN);
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save_state(dc);
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/* According to the table in the UA2011 manual, the only
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@ -2404,21 +2404,23 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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the NO_FAULT asis. We still need a helper for these,
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but we can just use the integer asi helper for them. */
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switch (size) {
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case 4:
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case MO_32:
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d64 = tcg_temp_new_i64();
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gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
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d32 = gen_dest_fpr_F(dc);
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tcg_gen_extrl_i64_i32(d32, d64);
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gen_store_fpr_F(dc, rd, d32);
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break;
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case 8:
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gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r_mop);
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case MO_64:
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gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr,
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r_asi, r_mop);
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break;
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case 16:
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case MO_128:
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d64 = tcg_temp_new_i64();
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gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop);
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tcg_gen_addi_tl(addr, addr, 8);
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gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r_mop);
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gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr,
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r_asi, r_mop);
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tcg_gen_mov_i64(cpu_fpr[rd / 2], d64);
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break;
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default:
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@ -2430,36 +2432,52 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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}
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static void __attribute__((unused))
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gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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{
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DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ));
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MemOp sz = ctz32(size);
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DisasASI da = get_asi(dc, insn, MO_TE | sz);
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gen_address_mask(dc, addr);
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gen_ldf_asi0(dc, &da, sz, addr, rd);
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}
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static void gen_stf_asi0(DisasContext *dc, DisasASI *da, MemOp orig_size,
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TCGv addr, int rd)
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{
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MemOp memop = da->memop;
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MemOp size = memop & MO_SIZE;
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TCGv_i32 d32;
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switch (da.type) {
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/* TODO: Use 128-bit load/store below. */
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if (size == MO_128) {
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memop = (memop & ~MO_SIZE) | MO_64;
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}
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switch (da->type) {
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case GET_ASI_EXCP:
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break;
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case GET_ASI_DIRECT:
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gen_address_mask(dc, addr);
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memop |= MO_ALIGN_4;
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switch (size) {
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case 4:
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case MO_32:
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d32 = gen_load_fpr_F(dc, rd);
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tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN);
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tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN);
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break;
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case 8:
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
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da.memop | MO_ALIGN_4);
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case MO_64:
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN_4);
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break;
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case 16:
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case MO_128:
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/* Only 4-byte alignment required. However, it is legal for the
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cpu to signal the alignment fault, and the OS trap handler is
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required to fix it up. Requiring 16-byte alignment here avoids
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having to probe the second page before performing the first
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write. */
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
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da.memop | MO_ALIGN_16);
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN_16);
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tcg_gen_addi_tl(addr, addr, 8);
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tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop);
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop);
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break;
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default:
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g_assert_not_reached();
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@ -2468,24 +2486,19 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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case GET_ASI_BLOCK:
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/* Valid for stdfa on aligned registers only. */
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if (size == 8 && (rd & 7) == 0) {
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MemOp memop;
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if (orig_size == MO_64 && (rd & 7) == 0) {
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TCGv eight;
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int i;
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gen_address_mask(dc, addr);
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/* The first operation checks required alignment. */
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memop = da.memop | MO_ALIGN_64;
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eight = tcg_constant_tl(8);
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for (i = 0; ; ++i) {
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr,
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da.mem_idx, memop);
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx,
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memop | (i == 0 ? MO_ALIGN_64 : 0));
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if (i == 7) {
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break;
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}
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tcg_gen_add_tl(addr, addr, eight);
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memop = da.memop;
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}
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} else {
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gen_exception(dc, TT_ILL_INSN);
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@ -2494,10 +2507,9 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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case GET_ASI_SHORT:
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/* Valid for stdfa only. */
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if (size == 8) {
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gen_address_mask(dc, addr);
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx,
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da.memop | MO_ALIGN);
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if (orig_size == MO_64) {
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tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx,
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memop | MO_ALIGN);
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} else {
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gen_exception(dc, TT_ILL_INSN);
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}
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@ -2512,6 +2524,16 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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}
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}
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static void __attribute__((unused))
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gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd)
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{
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MemOp sz = ctz32(size);
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DisasASI da = get_asi(dc, insn, MO_TE | sz);
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gen_address_mask(dc, addr);
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gen_stf_asi0(dc, &da, sz, addr, rd);
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}
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static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd)
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{
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TCGv hi = gen_dest_gpr(dc, rd);
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