target/riscv: Add AIA cpu feature
We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-id: 20220204174700.534953-7-anup@brainfault.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -78,7 +78,8 @@ enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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RISCV_FEATURE_EPMP,
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RISCV_FEATURE_MISA
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RISCV_FEATURE_MISA,
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RISCV_FEATURE_AIA
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};
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#define PRIV_VERSION_1_10_0 0x00011000
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