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hw/net/can: Introduce Xilinx Versal CANFD controller

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The Xilinx Versal CANFD controller is developed based on SocketCAN, QEMU CAN bus
implementation. Bus connection and socketCAN connection for each CAN module
can be set through command lines.

Signed-off-by: Vikram Garhwal <vikram.garhwal@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Vikram Garhwal 2023-06-06 10:19:30 +01:00 committed by Peter Maydell
parent eb2edc42b1
commit 32dbebcc7e
4 changed files with 2202 additions and 0 deletions
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1
hw/net/can/meson.build
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@ -5,3 +5,4 @@ softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'))
softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c'))
softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.c'))
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-canfd.c'))

7
hw/net/can/trace-events
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@ -7,3 +7,10 @@ xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MAS
xlnx_can_tx_data(uint32_t id, uint8_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
xlnx_can_rx_data(uint32_t id, uint32_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
xlnx_can_rx_discard(uint32_t status) "Controller is not enabled for bus communication. Status Register: 0x%08x"
# xlnx-versal-canfd.c
xlnx_canfd_update_irq(char *path, uint32_t isr, uint32_t ier, uint32_t irq) "%s: ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
xlnx_canfd_rx_fifo_filter_reject(char *path, uint32_t id, uint8_t dlc) "%s: Frame: ID: 0x%08x DLC: 0x%02x"
xlnx_canfd_rx_data(char *path, uint32_t id, uint8_t dlc, uint8_t flags) "%s: Frame: ID: 0x%08x DLC: 0x%02x CANFD Flag: 0x%02x"
xlnx_canfd_tx_data(char *path, uint32_t id, uint8_t dlc, uint8_t flgas) "%s: Frame: ID: 0x%08x DLC: 0x%02x CANFD Flag: 0x%02x"
xlnx_canfd_reset(char *path, uint32_t val) "%s: Resetting controller with value = 0x%08x"

2107
hw/net/can/xlnx-versal-canfd.c Normal file
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87
include/hw/net/xlnx-versal-canfd.h Normal file
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@ -0,0 +1,87 @@
/*
* QEMU model of the Xilinx Versal CANFD Controller.
*
* Copyright (c) 2023 Advanced Micro Devices, Inc.
*
* Written-by: Vikram Garhwal<vikram.garhwal@amd.com>
* Based on QEMU CANFD Device emulation implemented by Jin Yang, Deniz Eren and
* Pavel Pisa.
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#ifndef HW_CANFD_XILINX_H
#define HW_CANFD_XILINX_H
#include "hw/register.h"
#include "hw/ptimer.h"
#include "net/can_emu.h"
#include "hw/qdev-clock.h"
#define TYPE_XILINX_CANFD "xlnx.versal-canfd"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCANFDState, XILINX_CANFD)
#define NUM_REGS_PER_MSG_SPACE 18 /* 1 ID + 1 DLC + 16 Data(DW0 - DW15) regs. */
#define MAX_NUM_RX 64
#define OFFSET_RX1_DW15 (0x4144 / 4)
#define CANFD_TIMER_MAX 0xFFFFUL
#define CANFD_DEFAULT_CLOCK (25 * 1000 * 1000)
#define XLNX_VERSAL_CANFD_R_MAX (OFFSET_RX1_DW15 + \
((MAX_NUM_RX - 1) * NUM_REGS_PER_MSG_SPACE) + 1)
typedef struct XlnxVersalCANFDState {
SysBusDevice parent_obj;
MemoryRegion iomem;
qemu_irq irq_canfd_int;
qemu_irq irq_addr_err;
RegisterInfo reg_info[XLNX_VERSAL_CANFD_R_MAX];
RegisterAccessInfo *tx_regs;
RegisterAccessInfo *rx0_regs;
RegisterAccessInfo *rx1_regs;
RegisterAccessInfo *af_regs;
RegisterAccessInfo *txe_regs;
RegisterAccessInfo *rx_mailbox_regs;
RegisterAccessInfo *af_mask_regs_mailbox;
uint32_t regs[XLNX_VERSAL_CANFD_R_MAX];
ptimer_state *canfd_timer;
CanBusClientState bus_client;
CanBusState *canfdbus;
struct {
uint8_t rx0_fifo;
uint8_t rx1_fifo;
uint8_t tx_fifo;
bool enable_rx_fifo1;
uint32_t ext_clk_freq;
} cfg;
} XlnxVersalCANFDState;
typedef struct tx_ready_reg_info {
uint32_t can_id;
uint32_t reg_num;
} tx_ready_reg_info;
#endif