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target/riscv: rvv-1.0: Add Zve32f extension into RISC-V

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Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-12-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:14 +08:00 committed by Alistair Francis
parent bfefe406b7
commit 32e579b8c5
5 changed files with 7 additions and 4 deletions
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4
target/riscv/cpu.c
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@ -609,8 +609,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
}
set_vext_version(env, vext_version);
}
if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) {
error_setg(errp, "Zve64f extension depends upon RVF.");
if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) {
error_setg(errp, "Zve32f/Zve64f extension depends upon RVF.");
return;
}
if (cpu->cfg.ext_j) {

1
target/riscv/cpu.h
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@ -340,6 +340,7 @@ struct RISCVCPU {
bool ext_icsr;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zve32f;
bool ext_zve64f;
char *priv_spec;

2
target/riscv/cpu_helper.c
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@ -77,7 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
*pc = env->pc;
*cs_base = 0;
if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) {
if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
/*
* If env->vl equals to VLMAX, we can use generic vector operation
* expanders (GVEC) to accerlate the vector operations.

2
target/riscv/csr.c
View File

@ -51,7 +51,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
if (env->misa_ext & RVV ||
cpu->cfg.ext_zve64f) {
cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
#if !defined(CONFIG_USER_ONLY)
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;

2
target/riscv/translate.c
View File

@ -79,6 +79,7 @@ typedef struct DisasContext {
bool ext_ifencei;
bool ext_zfh;
bool ext_zfhmin;
bool ext_zve32f;
bool ext_zve64f;
bool hlsx;
/* vector extension */
@ -895,6 +896,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->ext_zfh = cpu->cfg.ext_zfh;
ctx->ext_zfhmin = cpu->cfg.ext_zfhmin;
ctx->ext_zve32f = cpu->cfg.ext_zve32f;
ctx->ext_zve64f = cpu->cfg.ext_zve64f;
ctx->vlen = cpu->cfg.vlen;
ctx->elen = cpu->cfg.elen;