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target/riscv: Convert the RISC-V exceptions to an enum 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: f191dcf08bf413a822e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-04-01 11:17:29 -04:00
parent 8a2aca3d79
commit 330d2ae32a
3 changed files with 26 additions and 24 deletions
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2
target/riscv/cpu.c
View File

@ -358,7 +358,7 @@ static void riscv_cpu_reset(DeviceState *dev)
env->pc = env->resetvec;
env->two_stage_lookup = false;
#endif
cs->exception_index = EXCP_NONE;
cs->exception_index = RISCV_EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
}

44
target/riscv/cpu_bits.h
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@ -504,27 +504,29 @@
#define DEFAULT_RSTVEC 0x1000
/* Exception causes */
#define EXCP_NONE -1 /* sentinel value */
#define RISCV_EXCP_INST_ADDR_MIS 0x0
#define RISCV_EXCP_INST_ACCESS_FAULT 0x1
#define RISCV_EXCP_ILLEGAL_INST 0x2
#define RISCV_EXCP_BREAKPOINT 0x3
#define RISCV_EXCP_LOAD_ADDR_MIS 0x4
#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
#define RISCV_EXCP_U_ECALL 0x8
#define RISCV_EXCP_S_ECALL 0x9
#define RISCV_EXCP_VS_ECALL 0xa
#define RISCV_EXCP_M_ECALL 0xb
#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
#define RISCV_EXCP_SEMIHOST 0x10
#define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
#define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
#define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16
#define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
typedef enum RISCVException {
RISCV_EXCP_NONE = -1, /* sentinel value */
RISCV_EXCP_INST_ADDR_MIS = 0x0,
RISCV_EXCP_INST_ACCESS_FAULT = 0x1,
RISCV_EXCP_ILLEGAL_INST = 0x2,
RISCV_EXCP_BREAKPOINT = 0x3,
RISCV_EXCP_LOAD_ADDR_MIS = 0x4,
RISCV_EXCP_LOAD_ACCESS_FAULT = 0x5,
RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6,
RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 0x7,
RISCV_EXCP_U_ECALL = 0x8,
RISCV_EXCP_S_ECALL = 0x9,
RISCV_EXCP_VS_ECALL = 0xa,
RISCV_EXCP_M_ECALL = 0xb,
RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
RISCV_EXCP_SEMIHOST = 0x10,
RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT = 0x15,
RISCV_EXCP_VIRT_INSTRUCTION_FAULT = 0x16,
RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT = 0x17,
} RISCVException;
#define RISCV_EXCP_INT_FLAG 0x80000000
#define RISCV_EXCP_INT_MASK 0x7fffffff

4
target/riscv/cpu_helper.c
View File

@ -72,7 +72,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
if (irqs) {
return ctz64(irqs); /* since non-zero */
} else {
return EXCP_NONE; /* indicates no pending interrupt */
return RISCV_EXCP_NONE; /* indicates no pending interrupt */
}
}
#endif
@ -1069,5 +1069,5 @@ void riscv_cpu_do_interrupt(CPUState *cs)
env->two_stage_lookup = false;
#endif
cs->exception_index = EXCP_NONE; /* mark handled to qemu */
cs->exception_index = RISCV_EXCP_NONE; /* mark handled to qemu */
}