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Monitor patches for 2022-12-19 

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Merge tag 'pull-monitor-2022-12-19' of https://repo.or.cz/qemu/armbru into staging

Monitor patches for 2022-12-19

# gpg: Signature made Mon 19 Dec 2022 15:23:44 GMT
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* tag 'pull-monitor-2022-12-19' of https://repo.or.cz/qemu/armbru:
  pci: Reject pcie_aer_inject_error -c with symbolic error status
  pci: Improve do_pcie_aer_inject_error()'s error messages
  pci: Rename hmp_pcie_aer_inject_error()'s local variable @err
  pci: Inline do_pcie_aer_inject_error() into its only caller
  pci: Move HMP command from hw/pci/pcie_aer.c to pci-hmp-cmds.c
  pci: Fix silent truncation of pcie_aer_inject_error argument
  pci: Move pcibus_dev_print() to pci-hmp-cmds.c
  pci: Deduplicate get_class_desc()
  pci: Build hw/pci/pci-hmp-cmds.c only when CONFIG_PCI
  pci: Make query-pci stub consistent with the real one
  pci: Move HMP commands from monitor/ to new hw/pci/pci-hmp-cmds.c
  pci: Move QMP commands to new hw/pci/pci-qmp-cmds.c
  pci: Clean up a few things checkpatch.pl would flag later on

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2022-12-19 16:12:59 +00:00
parent c15dc499cc e221cfac59
commit 33698d3abf
10 changed files with 478 additions and 443 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/pci/meson.build
View File

@ -5,6 +5,8 @@ pci_ss.add(files(
'pci.c',
'pci_bridge.c',
'pci_host.c',
'pci-hmp-cmds.c',
'pci-qmp-cmds.c',
'pcie_sriov.c',
'shpc.c',
'slotid_cap.c'

238
hw/pci/pci-hmp-cmds.c Normal file
View File

@ -0,0 +1,238 @@
/*
* HMP commands related to PCI
*
* Copyright IBM, Corp. 2011
*
* Authors:
* Anthony Liguori <aliguori@us.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "monitor/hmp.h"
#include "monitor/monitor.h"
#include "pci-internal.h"
#include "qapi/error.h"
#include "qapi/qmp/qdict.h"
#include "qapi/qapi-commands-pci.h"
#include "qemu/cutils.h"
static void hmp_info_pci_device(Monitor *mon, const PciDeviceInfo *dev)
{
PciMemoryRegionList *region;
monitor_printf(mon, " Bus %2" PRId64 ", ", dev->bus);
monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
dev->slot, dev->function);
monitor_printf(mon, " ");
if (dev->class_info->desc) {
monitor_puts(mon, dev->class_info->desc);
} else {
monitor_printf(mon, "Class %04" PRId64, dev->class_info->q_class);
}
monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
dev->id->vendor, dev->id->device);
if (dev->id->has_subsystem_vendor && dev->id->has_subsystem) {
monitor_printf(mon, " PCI subsystem %04" PRIx64 ":%04" PRIx64 "\n",
dev->id->subsystem_vendor, dev->id->subsystem);
}
if (dev->has_irq) {
monitor_printf(mon, " IRQ %" PRId64 ", pin %c\n",
dev->irq, (char)('A' + dev->irq_pin - 1));
}
if (dev->pci_bridge) {
monitor_printf(mon, " BUS %" PRId64 ".\n",
dev->pci_bridge->bus->number);
monitor_printf(mon, " secondary bus %" PRId64 ".\n",
dev->pci_bridge->bus->secondary);
monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
dev->pci_bridge->bus->subordinate);
monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
dev->pci_bridge->bus->io_range->base,
dev->pci_bridge->bus->io_range->limit);
monitor_printf(mon,
" memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
dev->pci_bridge->bus->memory_range->base,
dev->pci_bridge->bus->memory_range->limit);
monitor_printf(mon, " prefetchable memory range "
"[0x%08"PRIx64", 0x%08"PRIx64"]\n",
dev->pci_bridge->bus->prefetchable_range->base,
dev->pci_bridge->bus->prefetchable_range->limit);
}
for (region = dev->regions; region; region = region->next) {
uint64_t addr, size;
addr = region->value->address;
size = region->value->size;
monitor_printf(mon, " BAR%" PRId64 ": ", region->value->bar);
if (!strcmp(region->value->type, "io")) {
monitor_printf(mon, "I/O at 0x%04" PRIx64
" [0x%04" PRIx64 "].\n",
addr, addr + size - 1);
} else {
monitor_printf(mon, "%d bit%s memory at 0x%08" PRIx64
" [0x%08" PRIx64 "].\n",
region->value->mem_type_64 ? 64 : 32,
region->value->prefetch ? " prefetchable" : "",
addr, addr + size - 1);
}
}
monitor_printf(mon, " id \"%s\"\n", dev->qdev_id);
if (dev->pci_bridge) {
if (dev->pci_bridge->has_devices) {
PciDeviceInfoList *cdev;
for (cdev = dev->pci_bridge->devices; cdev; cdev = cdev->next) {
hmp_info_pci_device(mon, cdev->value);
}
}
}
}
void hmp_info_pci(Monitor *mon, const QDict *qdict)
{
PciInfoList *info_list, *info;
info_list = qmp_query_pci(&error_abort);
for (info = info_list; info; info = info->next) {
PciDeviceInfoList *dev;
for (dev = info->value->devices; dev; dev = dev->next) {
hmp_info_pci_device(mon, dev->value);
}
}
qapi_free_PciInfoList(info_list);
}
void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
PCIDevice *d = (PCIDevice *)dev;
int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
const pci_class_desc *desc = get_class_desc(class);
char ctxt[64];
PCIIORegion *r;
int i;
if (desc->desc) {
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
} else {
snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
}
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
"pci id %04x:%04x (sub %04x:%04x)\n",
indent, "", ctxt, pci_dev_bus_num(d),
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
pci_get_word(d->config + PCI_VENDOR_ID),
pci_get_word(d->config + PCI_DEVICE_ID),
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
pci_get_word(d->config + PCI_SUBSYSTEM_ID));
for (i = 0; i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
if (!r->size) {
continue;
}
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
" [0x%"FMT_PCIBUS"]\n",
indent, "",
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
r->addr, r->addr + r->size - 1);
}
}
void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict)
{
Error *err = NULL;
const char *id = qdict_get_str(qdict, "id");
const char *error_name;
uint32_t error_status;
unsigned int num;
bool correctable;
PCIDevice *dev;
PCIEAERErr aer_err;
int ret;
ret = pci_qdev_find_device(id, &dev);
if (ret == -ENODEV) {
error_setg(&err, "device '%s' not found", id);
goto out;
}
if (ret < 0 || !pci_is_express(dev)) {
error_setg(&err, "device '%s' is not a PCIe device", id);
goto out;
}
error_name = qdict_get_str(qdict, "error_status");
if (pcie_aer_parse_error_string(error_name, &error_status, &correctable)) {
if (qemu_strtoui(error_name, NULL, 0, &num) < 0) {
error_setg(&err, "invalid error status value '%s'", error_name);
goto out;
}
error_status = num;
correctable = qdict_get_try_bool(qdict, "correctable", false);
} else {
if (qdict_haskey(qdict, "correctable")) {
error_setg(&err, "-c is only valid with numeric error status");
goto out;
}
}
aer_err.status = error_status;
aer_err.source_id = pci_requester_id(dev);
aer_err.flags = 0;
if (correctable) {
aer_err.flags |= PCIE_AER_ERR_IS_CORRECTABLE;
}
if (qdict_get_try_bool(qdict, "advisory_non_fatal", false)) {
aer_err.flags |= PCIE_AER_ERR_MAYBE_ADVISORY;
}
if (qdict_haskey(qdict, "header0")) {
aer_err.flags |= PCIE_AER_ERR_HEADER_VALID;
}
if (qdict_haskey(qdict, "prefix0")) {
aer_err.flags |= PCIE_AER_ERR_TLP_PREFIX_PRESENT;
}
aer_err.header[0] = qdict_get_try_int(qdict, "header0", 0);
aer_err.header[1] = qdict_get_try_int(qdict, "header1", 0);
aer_err.header[2] = qdict_get_try_int(qdict, "header2", 0);
aer_err.header[3] = qdict_get_try_int(qdict, "header3", 0);
aer_err.prefix[0] = qdict_get_try_int(qdict, "prefix0", 0);
aer_err.prefix[1] = qdict_get_try_int(qdict, "prefix1", 0);
aer_err.prefix[2] = qdict_get_try_int(qdict, "prefix2", 0);
aer_err.prefix[3] = qdict_get_try_int(qdict, "prefix3", 0);
ret = pcie_aer_inject_error(dev, &aer_err);
if (ret < 0) {
error_setg_errno(&err, -ret, "failed to inject error");
goto out;
}
monitor_printf(mon, "OK id: %s root bus: %s, bus: %x devfn: %x.%x\n",
id, pci_root_bus_path(dev), pci_dev_bus_num(dev),
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
out:
hmp_handle_error(mon, err);
}

25
hw/pci/pci-internal.h Normal file
View File

@ -0,0 +1,25 @@
#ifndef HW_PCI_PCI_INTERNAL_H
#define HW_PCI_PCI_INTERNAL_H
#include "qemu/queue.h"
typedef struct {
uint16_t class;
const char *desc;
const char *fw_name;
uint16_t fw_ign_bits;
} pci_class_desc;
typedef QLIST_HEAD(, PCIHostState) PCIHostStateList;
extern PCIHostStateList pci_host_bridges;
const pci_class_desc *get_class_desc(int class);
PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
int pcie_aer_parse_error_string(const char *error_name,
uint32_t *status, bool *correctable);
int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err);
#endif

199
hw/pci/pci-qmp-cmds.c Normal file
View File

@ -0,0 +1,199 @@
/*
* QMP commands related to PCI
*
* Copyright (c) 2004 Fabrice Bellard
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "pci-internal.h"
#include "qapi/qapi-commands-pci.h"
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
{
PciMemoryRegionList *head = NULL, **tail = &head;
int i;
for (i = 0; i < PCI_NUM_REGIONS; i++) {
const PCIIORegion *r = &dev->io_regions[i];
PciMemoryRegion *region;
if (!r->size) {
continue;
}
region = g_malloc0(sizeof(*region));
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
region->type = g_strdup("io");
} else {
region->type = g_strdup("memory");
region->has_prefetch = true;
region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
region->has_mem_type_64 = true;
region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
}
region->bar = i;
region->address = r->addr;
region->size = r->size;
QAPI_LIST_APPEND(tail, region);
}
return head;
}
static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
int bus_num)
{
PciBridgeInfo *info;
PciMemoryRange *range;
info = g_new0(PciBridgeInfo, 1);
info->bus = g_new0(PciBusInfo, 1);
info->bus->number = dev->config[PCI_PRIMARY_BUS];
info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
range = info->bus->io_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
if (dev->config[PCI_SECONDARY_BUS] != 0) {
PCIBus *child_bus = pci_find_bus_nr(bus,
dev->config[PCI_SECONDARY_BUS]);
if (child_bus) {
info->has_devices = true;
info->devices = qmp_query_pci_devices(child_bus,
dev->config[PCI_SECONDARY_BUS]);
}
}
return info;
}
static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
int bus_num)
{
const pci_class_desc *desc;
PciDeviceInfo *info;
uint8_t type;
int class;
info = g_new0(PciDeviceInfo, 1);
info->bus = bus_num;
info->slot = PCI_SLOT(dev->devfn);
info->function = PCI_FUNC(dev->devfn);
info->class_info = g_new0(PciDeviceClass, 1);
class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
info->class_info->q_class = class;
desc = get_class_desc(class);
if (desc->desc) {
info->class_info->desc = g_strdup(desc->desc);
}
info->id = g_new0(PciDeviceId, 1);
info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
info->regions = qmp_query_pci_regions(dev);
info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
info->irq_pin = dev->config[PCI_INTERRUPT_PIN];
if (dev->config[PCI_INTERRUPT_PIN] != 0) {
info->has_irq = true;
info->irq = dev->config[PCI_INTERRUPT_LINE];
}
type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
if (type == PCI_HEADER_TYPE_BRIDGE) {
info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
} else if (type == PCI_HEADER_TYPE_NORMAL) {
info->id->has_subsystem = info->id->has_subsystem_vendor = true;
info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID);
info->id->subsystem_vendor =
pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID);
} else if (type == PCI_HEADER_TYPE_CARDBUS) {
info->id->has_subsystem = info->id->has_subsystem_vendor = true;
info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID);
info->id->subsystem_vendor =
pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID);
}
return info;
}
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
{
PciDeviceInfoList *head = NULL, **tail = &head;
PCIDevice *dev;
int devfn;
for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
dev = bus->devices[devfn];
if (dev) {
QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num));
}
}
return head;
}
static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
{
PciInfo *info = NULL;
bus = pci_find_bus_nr(bus, bus_num);
if (bus) {
info = g_malloc0(sizeof(*info));
info->bus = bus_num;
info->devices = qmp_query_pci_devices(bus, bus_num);
}
return info;
}
PciInfoList *qmp_query_pci(Error **errp)
{
PciInfoList *head = NULL, **tail = &head;
PCIHostState *host_bridge;
QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
QAPI_LIST_APPEND(tail,
qmp_query_pci_bus(host_bridge->bus,
pci_bus_num(host_bridge->bus)));
}
return head;
}

9
hw/pci/pci-stub.c
View File

@ -19,11 +19,9 @@
*/
#include "qemu/osdep.h"
#include "sysemu/sysemu.h"
#include "monitor/monitor.h"
#include "qapi/error.h"
#include "monitor/hmp.h"
#include "qapi/qapi-commands-pci.h"
#include "qapi/qmp/qerror.h"
#include "hw/pci/pci.h"
#include "hw/pci/msi.h"
#include "hw/pci/msix.h"
@ -33,10 +31,13 @@ bool pci_available;
PciInfoList *qmp_query_pci(Error **errp)
{
error_setg(errp, QERR_UNSUPPORTED);
return NULL;
}
void hmp_info_pci(Monitor *mon, const QDict *qdict)
{
}
void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict)
{
monitor_printf(mon, "PCI devices not supported\n");

224
hw/pci/pci.c
View File

@ -34,7 +34,6 @@
#include "hw/qdev-properties-system.h"
#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "net/net.h"
#include "sysemu/numa.h"
#include "sysemu/sysemu.h"
@ -47,8 +46,8 @@
#include "hw/hotplug.h"
#include "hw/boards.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-pci.h"
#include "qemu/cutils.h"
#include "pci-internal.h"
//#define DEBUG_PCI
#ifdef DEBUG_PCI
@ -59,7 +58,6 @@
bool pci_available = true;
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *pcibus_get_dev_path(DeviceState *dev);
static char *pcibus_get_fw_dev_path(DeviceState *dev);
static void pcibus_reset(BusState *qbus);
@ -234,7 +232,6 @@ static const TypeInfo cxl_bus_info = {
.class_init = pcie_bus_class_init,
};
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
static void pci_update_mappings(PCIDevice *d);
static void pci_irq_handler(void *opaque, int irq_num, int level);
static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **);
@ -243,7 +240,7 @@ static void pci_del_option_rom(PCIDevice *pdev);
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
static QLIST_HEAD(, PCIHostState) pci_host_bridges;
PCIHostStateList pci_host_bridges;
int pci_bar(PCIDevice *d, int reg)
{
@ -1662,13 +1659,6 @@ int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin)
/***********************************************************/
/* monitor info on PCI */
typedef struct {
uint16_t class;
const char *desc;
const char *fw_name;
uint16_t fw_ign_bits;
} pci_class_desc;
static const pci_class_desc pci_class_descriptions[] =
{
{ 0x0001, "VGA controller", "display"},
@ -1776,7 +1766,7 @@ void pci_for_each_device(PCIBus *bus, int bus_num,
}
}
static const pci_class_desc *get_class_desc(int class)
const pci_class_desc *get_class_desc(int class)
{
const pci_class_desc *desc;
@ -1788,174 +1778,6 @@ static const pci_class_desc *get_class_desc(int class)
return desc;
}
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
{
PciMemoryRegionList *head = NULL, **tail = &head;
int i;
for (i = 0; i < PCI_NUM_REGIONS; i++) {
const PCIIORegion *r = &dev->io_regions[i];
PciMemoryRegion *region;
if (!r->size) {
continue;
}
region = g_malloc0(sizeof(*region));
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
region->type = g_strdup("io");
} else {
region->type = g_strdup("memory");
region->has_prefetch = true;
region->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
region->has_mem_type_64 = true;
region->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
}
region->bar = i;
region->address = r->addr;
region->size = r->size;
QAPI_LIST_APPEND(tail, region);
}
return head;
}
static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
int bus_num)
{
PciBridgeInfo *info;
PciMemoryRange *range;
info = g_new0(PciBridgeInfo, 1);
info->bus = g_new0(PciBusInfo, 1);
info->bus->number = dev->config[PCI_PRIMARY_BUS];
info->bus->secondary = dev->config[PCI_SECONDARY_BUS];
info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS];
range = info->bus->io_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
range = info->bus->memory_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1);
range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
if (dev->config[PCI_SECONDARY_BUS] != 0) {
PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
if (child_bus) {
info->has_devices = true;
info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
}
}
return info;
}
static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
int bus_num)
{
const pci_class_desc *desc;
PciDeviceInfo *info;
uint8_t type;
int class;
info = g_new0(PciDeviceInfo, 1);
info->bus = bus_num;
info->slot = PCI_SLOT(dev->devfn);
info->function = PCI_FUNC(dev->devfn);
info->class_info = g_new0(PciDeviceClass, 1);
class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
info->class_info->q_class = class;
desc = get_class_desc(class);
if (desc->desc) {
info->class_info->desc = g_strdup(desc->desc);
}
info->id = g_new0(PciDeviceId, 1);
info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID);
info->regions = qmp_query_pci_regions(dev);
info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
info->irq_pin = dev->config[PCI_INTERRUPT_PIN];
if (dev->config[PCI_INTERRUPT_PIN] != 0) {
info->has_irq = true;
info->irq = dev->config[PCI_INTERRUPT_LINE];
}
type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
if (type == PCI_HEADER_TYPE_BRIDGE) {
info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
} else if (type == PCI_HEADER_TYPE_NORMAL) {
info->id->has_subsystem = info->id->has_subsystem_vendor = true;
info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID);
info->id->subsystem_vendor =
pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID);
} else if (type == PCI_HEADER_TYPE_CARDBUS) {
info->id->has_subsystem = info->id->has_subsystem_vendor = true;
info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID);
info->id->subsystem_vendor =
pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID);
}
return info;
}
static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
{
PciDeviceInfoList *head = NULL, **tail = &head;
PCIDevice *dev;
int devfn;
for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
dev = bus->devices[devfn];
if (dev) {
QAPI_LIST_APPEND(tail, qmp_query_pci_device(dev, bus, bus_num));
}
}
return head;
}
static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
{
PciInfo *info = NULL;
bus = pci_find_bus_nr(bus, bus_num);
if (bus) {
info = g_malloc0(sizeof(*info));
info->bus = bus_num;
info->devices = qmp_query_pci_devices(bus, bus_num);
}
return info;
}
PciInfoList *qmp_query_pci(Error **errp)
{
PciInfoList *head = NULL, **tail = &head;
PCIHostState *host_bridge;
QLIST_FOREACH(host_bridge, &pci_host_bridges, next) {
QAPI_LIST_APPEND(tail,
qmp_query_pci_bus(host_bridge->bus,
pci_bus_num(host_bridge->bus)));
}
return head;
}
/* Initialize a PCI NIC. */
PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
const char *default_model,
@ -2104,7 +1926,7 @@ static bool pci_root_bus_in_range(PCIBus *bus, int bus_num)
return false;
}
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
{
PCIBus *sec;
@ -2582,44 +2404,6 @@ uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
return pci_find_capability_list(pdev, cap_id, NULL);
}
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
{
PCIDevice *d = (PCIDevice *)dev;
const pci_class_desc *desc;
char ctxt[64];
PCIIORegion *r;
int i, class;
class = pci_get_word(d->config + PCI_CLASS_DEVICE);
desc = pci_class_descriptions;
while (desc->desc && class != desc->class)
desc++;
if (desc->desc) {
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
} else {
snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
}
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
"pci id %04x:%04x (sub %04x:%04x)\n",
indent, "", ctxt, pci_dev_bus_num(d),
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
pci_get_word(d->config + PCI_VENDOR_ID),
pci_get_word(d->config + PCI_DEVICE_ID),
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
pci_get_word(d->config + PCI_SUBSYSTEM_ID));
for (i = 0; i < PCI_NUM_REGIONS; i++) {
r = &d->io_regions[i];
if (!r->size)
continue;
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
" [0x%"FMT_PCIBUS"]\n",
indent, "",
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
r->addr, r->addr + r->size - 1);
}
}
static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
{
PCIDevice *d = (PCIDevice *)dev;

113
hw/pci/pcie_aer.c
View File

@ -19,17 +19,14 @@
*/
#include "qemu/osdep.h"
#include "sysemu/sysemu.h"
#include "qapi/qmp/qdict.h"
#include "migration/vmstate.h"
#include "monitor/monitor.h"
#include "hw/pci/pci_bridge.h"
#include "hw/pci/pcie.h"
#include "hw/pci/msix.h"
#include "hw/pci/msi.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pcie_regs.h"
#include "qapi/error.h"
#include "pci-internal.h"
//#define DEBUG_PCIE
#ifdef DEBUG_PCIE
@ -44,13 +41,6 @@
#define PCI_ERR_SRC_COR_OFFS 0
#define PCI_ERR_SRC_UNCOR_OFFS 2
typedef struct PCIEErrorDetails {
const char *id;
const char *root_bus;
int bus;
int devfn;
} PCIEErrorDetails;
/* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
{
@ -631,7 +621,7 @@ static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal)
* Figure 6-2: Flowchart Showing Sequence of Device Error Signaling and Logging
* Operations
*/
static int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err)
int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err)
{
uint8_t *aer_cap = NULL;
uint16_t devctl = 0;
@ -933,8 +923,8 @@ static const struct PCIEAERErrorName pcie_aer_error_list[] = {
},
};
static int pcie_aer_parse_error_string(const char *error_name,
uint32_t *status, bool *correctable)
int pcie_aer_parse_error_string(const char *error_name,
uint32_t *status, bool *correctable)
{
int i;
@ -950,98 +940,3 @@ static int pcie_aer_parse_error_string(const char *error_name,
}
return -EINVAL;
}
/*
* Inject an error described by @qdict.
* On success, set @details to show where error was sent.
* Return negative errno if injection failed and a message was emitted.
*/
static int do_pcie_aer_inject_error(Monitor *mon,
const QDict *qdict,
PCIEErrorDetails *details)
{
const char *id = qdict_get_str(qdict, "id");
const char *error_name;
uint32_t error_status;
bool correctable;
PCIDevice *dev;
PCIEAERErr err;
int ret;
ret = pci_qdev_find_device(id, &dev);
if (ret < 0) {
monitor_printf(mon,
"id or pci device path is invalid or device not "
"found. %s\n", id);
return ret;
}
if (!pci_is_express(dev)) {
monitor_printf(mon, "the device doesn't support pci express. %s\n",
id);
return -ENOSYS;
}
error_name = qdict_get_str(qdict, "error_status");
if (pcie_aer_parse_error_string(error_name, &error_status, &correctable)) {
char *e = NULL;
error_status = strtoul(error_name, &e, 0);
correctable = qdict_get_try_bool(qdict, "correctable", false);
if (!e || *e != '\0') {
monitor_printf(mon, "invalid error status value. \"%s\"",
error_name);
return -EINVAL;
}
}
err.status = error_status;
err.source_id = pci_requester_id(dev);
err.flags = 0;
if (correctable) {
err.flags |= PCIE_AER_ERR_IS_CORRECTABLE;
}
if (qdict_get_try_bool(qdict, "advisory_non_fatal", false)) {
err.flags |= PCIE_AER_ERR_MAYBE_ADVISORY;
}
if (qdict_haskey(qdict, "header0")) {
err.flags |= PCIE_AER_ERR_HEADER_VALID;
}
if (qdict_haskey(qdict, "prefix0")) {
err.flags |= PCIE_AER_ERR_TLP_PREFIX_PRESENT;
}
err.header[0] = qdict_get_try_int(qdict, "header0", 0);
err.header[1] = qdict_get_try_int(qdict, "header1", 0);
err.header[2] = qdict_get_try_int(qdict, "header2", 0);
err.header[3] = qdict_get_try_int(qdict, "header3", 0);
err.prefix[0] = qdict_get_try_int(qdict, "prefix0", 0);
err.prefix[1] = qdict_get_try_int(qdict, "prefix1", 0);
err.prefix[2] = qdict_get_try_int(qdict, "prefix2", 0);
err.prefix[3] = qdict_get_try_int(qdict, "prefix3", 0);
ret = pcie_aer_inject_error(dev, &err);
if (ret < 0) {
monitor_printf(mon, "failed to inject error: %s\n",
strerror(-ret));
return ret;
}
details->id = id;
details->root_bus = pci_root_bus_path(dev);
details->bus = pci_dev_bus_num(dev);
details->devfn = dev->devfn;
return 0;
}
void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict)
{
PCIEErrorDetails data;
if (do_pcie_aer_inject_error(mon, qdict, &data) < 0) {
return;
}
monitor_printf(mon, "OK id: %s root bus: %s, bus: %x devfn: %x.%x\n",
data.id, data.root_bus, data.bus,
PCI_SLOT(data.devfn), PCI_FUNC(data.devfn));
}

1
include/monitor/hmp.h
View File

@ -143,5 +143,6 @@ void hmp_info_vcpu_dirty_limit(Monitor *mon, const QDict *qdict);
void hmp_human_readable_text_helper(Monitor *mon,
HumanReadableText *(*qmp_handler)(Error **));
void hmp_info_stats(Monitor *mon, const QDict *qdict);
void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict);
#endif

3
include/sysemu/sysemu.h
View File

@ -61,9 +61,6 @@ extern int nb_option_roms;
extern const char *prom_envs[MAX_PROM_ENVS];
extern unsigned int nb_prom_envs;
/* pcie aer error injection */
void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict);
/* serial ports */
/* Return the Chardev for serial port i, or NULL if none */

107
monitor/hmp-cmds.c
View File

@ -37,7 +37,6 @@
#include "qapi/qapi-commands-migration.h"
#include "qapi/qapi-commands-misc.h"
#include "qapi/qapi-commands-net.h"
#include "qapi/qapi-commands-pci.h"
#include "qapi/qapi-commands-rocker.h"
#include "qapi/qapi-commands-run-state.h"
#include "qapi/qapi-commands-stats.h"
@ -698,89 +697,6 @@ void hmp_info_balloon(Monitor *mon, const QDict *qdict)
qapi_free_BalloonInfo(info);
}
static void hmp_info_pci_device(Monitor *mon, const PciDeviceInfo *dev)
{
PciMemoryRegionList *region;
monitor_printf(mon, " Bus %2" PRId64 ", ", dev->bus);
monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
dev->slot, dev->function);
monitor_printf(mon, " ");
if (dev->class_info->desc) {
monitor_puts(mon, dev->class_info->desc);
} else {
monitor_printf(mon, "Class %04" PRId64, dev->class_info->q_class);
}
monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
dev->id->vendor, dev->id->device);
if (dev->id->has_subsystem_vendor && dev->id->has_subsystem) {
monitor_printf(mon, " PCI subsystem %04" PRIx64 ":%04" PRIx64 "\n",
dev->id->subsystem_vendor, dev->id->subsystem);
}
if (dev->has_irq) {
monitor_printf(mon, " IRQ %" PRId64 ", pin %c\n",
dev->irq, (char)('A' + dev->irq_pin - 1));
}
if (dev->pci_bridge) {
monitor_printf(mon, " BUS %" PRId64 ".\n",
dev->pci_bridge->bus->number);
monitor_printf(mon, " secondary bus %" PRId64 ".\n",
dev->pci_bridge->bus->secondary);
monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
dev->pci_bridge->bus->subordinate);
monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
dev->pci_bridge->bus->io_range->base,
dev->pci_bridge->bus->io_range->limit);
monitor_printf(mon,
" memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
dev->pci_bridge->bus->memory_range->base,
dev->pci_bridge->bus->memory_range->limit);
monitor_printf(mon, " prefetchable memory range "
"[0x%08"PRIx64", 0x%08"PRIx64"]\n",
dev->pci_bridge->bus->prefetchable_range->base,
dev->pci_bridge->bus->prefetchable_range->limit);
}
for (region = dev->regions; region; region = region->next) {
uint64_t addr, size;
addr = region->value->address;
size = region->value->size;
monitor_printf(mon, " BAR%" PRId64 ": ", region->value->bar);
if (!strcmp(region->value->type, "io")) {
monitor_printf(mon, "I/O at 0x%04" PRIx64
" [0x%04" PRIx64 "].\n",
addr, addr + size - 1);
} else {
monitor_printf(mon, "%d bit%s memory at 0x%08" PRIx64
" [0x%08" PRIx64 "].\n",
region->value->mem_type_64 ? 64 : 32,
region->value->prefetch ? " prefetchable" : "",
addr, addr + size - 1);
}
}
monitor_printf(mon, " id \"%s\"\n", dev->qdev_id);
if (dev->pci_bridge) {
if (dev->pci_bridge->has_devices) {
PciDeviceInfoList *cdev;
for (cdev = dev->pci_bridge->devices; cdev; cdev = cdev->next) {
hmp_info_pci_device(mon, cdev->value);
}
}
}
}
static int hmp_info_pic_foreach(Object *obj, void *opaque)
{
InterruptStatsProvider *intc;
@ -807,29 +723,6 @@ void hmp_info_pic(Monitor *mon, const QDict *qdict)
hmp_info_pic_foreach, mon);
}
void hmp_info_pci(Monitor *mon, const QDict *qdict)
{
PciInfoList *info_list, *info;
Error *err = NULL;
info_list = qmp_query_pci(&err);
if (err) {
monitor_printf(mon, "PCI devices not supported\n");
error_free(err);
return;
}
for (info = info_list; info; info = info->next) {
PciDeviceInfoList *dev;
for (dev = info->value->devices; dev; dev = dev->next) {
hmp_info_pci_device(mon, dev->value);
}
}
qapi_free_PciInfoList(info_list);
}
void hmp_info_tpm(Monitor *mon, const QDict *qdict)
{
#ifdef CONFIG_TPM