OpenE2K/qemu-e2k
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pcie_aer: Convert pcie_aer_init to Error

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When user specify invalid value for property aer_log_max, device should
fail to create, and report appropriate message.

Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Acked-by: Dmitry Fleytman <dmitry@daynix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Cao jin 2016-12-21 16:21:30 +08:00 committed by Michael S. Tsirkin
parent 02ed3e7c16
commit 33848ceed7
6 changed files with 16 additions and 16 deletions
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2
hw/net/e1000e.c
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@ -472,7 +472,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
hw_error("Failed to initialize PM capability"); hw_error("Failed to initialize PM capability");
} }
if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF) < 0) { if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) {
hw_error("Failed to initialize AER capability"); hw_error("Failed to initialize AER capability");
} }

3
hw/pci-bridge/ioh3420.c
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@ -135,8 +135,9 @@ static int ioh3420_initfn(PCIDevice *d)
goto err_pcie_cap; goto err_pcie_cap;
} }
rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF); rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF, &err);
if (rc < 0) { if (rc < 0) {
error_report_err(err);
goto err; goto err;
} }
pcie_aer_root_init(d); pcie_aer_root_init(d);

3
hw/pci-bridge/xio3130_downstream.c
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@ -97,8 +97,9 @@ static int xio3130_downstream_initfn(PCIDevice *d)
goto err_pcie_cap; goto err_pcie_cap;
} }
rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
if (rc < 0) { if (rc < 0) {
error_report_err(err);
goto err; goto err;
} }

3
hw/pci-bridge/xio3130_upstream.c
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@ -85,8 +85,9 @@ static int xio3130_upstream_initfn(PCIDevice *d)
pcie_cap_flr_init(d); pcie_cap_flr_init(d);
pcie_cap_deverr_init(d); pcie_cap_deverr_init(d);
rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF); rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
if (rc < 0) { if (rc < 0) {
error_report_err(err);
goto err; goto err;
} }

17
hw/pci/pcie_aer.c
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@ -29,6 +29,7 @@
#include "hw/pci/msi.h" #include "hw/pci/msi.h"
#include "hw/pci/pci_bus.h" #include "hw/pci/pci_bus.h"
#include "hw/pci/pcie_regs.h" #include "hw/pci/pcie_regs.h"
#include "qapi/error.h"
//#define DEBUG_PCIE //#define DEBUG_PCIE
#ifdef DEBUG_PCIE #ifdef DEBUG_PCIE
@ -96,21 +97,17 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
aer_log->log_num = 0; aer_log->log_num = 0;
} }
int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size) int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
Error **errp)
{ {
PCIExpressDevice *exp;
pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER, pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
offset, size); offset, size);
exp = &dev->exp; dev->exp.aer_cap = offset;
exp->aer_cap = offset;
/* log_max is property */ /* clip down the value to avoid unreasonable memory usage */
if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT;
}
/* clip down the value to avoid unreasobale memory usage */
if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) { if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
error_setg(errp, "Invalid aer_log_max %d. The max number of aer log "
"is %d", dev->exp.aer_log.log_max, PCIE_AER_LOG_MAX_LIMIT);
return -EINVAL; return -EINVAL;
} }
dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] * dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] *

4
include/hw/pci/pcie_aer.h
View File

@ -44,7 +44,6 @@ struct PCIEAERLog {
*/ */
#define PCIE_AER_LOG_MAX_DEFAULT 8 #define PCIE_AER_LOG_MAX_DEFAULT 8
#define PCIE_AER_LOG_MAX_LIMIT 128 #define PCIE_AER_LOG_MAX_LIMIT 128
#define PCIE_AER_LOG_MAX_UNSET 0xffff
uint16_t log_max; uint16_t log_max;
/* Error log. log_max-sized array */ /* Error log. log_max-sized array */
@ -87,7 +86,8 @@ struct PCIEAERErr {
extern const VMStateDescription vmstate_pcie_aer_log; extern const VMStateDescription vmstate_pcie_aer_log;
int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size); int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
Error **errp);
void pcie_aer_exit(PCIDevice *dev); void pcie_aer_exit(PCIDevice *dev);
void pcie_aer_write_config(PCIDevice *dev, void pcie_aer_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len); uint32_t addr, uint32_t val, int len);