target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation
We distinguish write-only by passing ret_value as NULL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210823195529.560295-17-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -937,9 +937,12 @@ static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
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/* Shift the S bits to their VS bit location in mip */
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int ret = rmw_mip(env, 0, ret_value, new_value << 1,
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(write_mask << 1) & vsip_writable_mask & env->hideleg);
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*ret_value &= VS_MODE_INTERRUPTS;
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/* Shift the VS bits to their S bit location in vsip */
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*ret_value >>= 1;
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if (ret_value) {
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*ret_value &= VS_MODE_INTERRUPTS;
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/* Shift the VS bits to their S bit location in vsip */
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*ret_value >>= 1;
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}
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return ret;
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}
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@ -956,7 +959,9 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
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write_mask & env->mideleg & sip_writable_mask);
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}
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*ret_value &= env->mideleg;
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if (ret_value) {
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*ret_value &= env->mideleg;
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}
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return ret;
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}
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@ -1072,8 +1077,9 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
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int ret = rmw_mip(env, 0, ret_value, new_value,
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write_mask & hvip_writable_mask);
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*ret_value &= hvip_writable_mask;
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if (ret_value) {
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*ret_value &= hvip_writable_mask;
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}
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return ret;
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}
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@ -1084,8 +1090,9 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno,
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int ret = rmw_mip(env, 0, ret_value, new_value,
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write_mask & hip_writable_mask);
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*ret_value &= hip_writable_mask;
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if (ret_value) {
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*ret_value &= hip_writable_mask;
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}
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return ret;
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}
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